Overcurrent protective device

ABSTRACT

An overcurrent protective device of the time delay type is provided which is responsive to the current in an alternating current circuit which is being protected. When the instantaneous current exceeds a predetermined value as sensed by a level detecting means, the protective device produces an output after a predetermined time delay which may be of a fixed duration or which may vary inversely with the magnitude of the current being sensed. If the instantaneous current decreases below the predetermined value before the end of the predetermined time delay and remains below the predetermined value, the level detecting means after a relatively short time period or interval actuates or resets the protective device to an operating condition which corresponds to the beginning of whatever predetermined time delay is provided in the operation of the overall protective device.

I United States Patent 1 1 3,590,326

172| Inventor John D. Willon 3.262.017 7/1966 Ashenden et a1. 317/36 X Portsmouth, England 3,329,870 7/1967 Viney et al 317/36 [21] Appl. No. 47.624 3.419.757 12/1968 Steen 3l7/36 523 g Primary Examiner-James D. Trammell Assign m Elam: m Attorneys-A. T. Stratton and C. L. Mel-tale Pittsburgh, Pa. oi 'Pmmm ABSTRACT: An overcurrent protective device of the time now abandoned delay type is provided which is responsive to the current in an alternating current circuit which is being protected. When the instantaneous current exceeds a predetermined value as [54) OVERCURRENT PROTECTIVE DEVICE sensed by a level detecting means, the protective device produces an output afier a predetermined time delay which 20 Claims, 4 Drawing Figs.

may be of a fixed duration or which may vary inversely WM Cl 317/361 the magnitude of the current being sensed. 1f the instantane- 3 |7/|42 320/1 ous current decreases below the predetermined value before Cl 45/18 the end of the predetermined time delay and remains below olsardl the predetermined value the [eye] detecting means afler a 3 7/36 relatively short time period or interval actuates or resets the protective device to an operating condition which cor- [s6l Refemm Cm responds to the beginning of whatever predetermined time UNITED STATES PATENTS delay is provided in the operation of the overall protective Re. 25.762 4/1965 Kotheimer 317/36 device.

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INVENTOR John D. Watson BY M FIGS.

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OVERCURRENT PROTECTIVE DEVICE This application is a continuation of application Ser. No. 765,582, filed Oct. 7, I968 now abandoned.

Cross References to Related Applications Certain features of the protective device disclosed in the present application are disclosed and claimed in copending application Ser. No. 765,583, filed Oct. 7, I968 by .I. D. Watson, copending application Ser. No. 765,584, filed Oct. 7, 1968 by .l. D. Watson, F. 0. Johnson and F. T. Thompson and copending application Ser. No. 765,552, filed Oct. 7, 1968 by W. H. South and .l. H. Taylor which are all assigned to the same assignee as the present application.

Background of the Invention This invention relates to overcurrent protective relay devices of the time delay type and more particularly to means for detecting the level of an overcurrent in an electrical circuit which is being protected.

In the past, overcurrent protective devices, particularly those of the static type, have provided means for rectifying and filtering an alternating signal which is derived from the 211' ternating current in the circuit being protected to obtain a filtcred, unidirectional output signal which is then applied to a level detecting circuit or means which responds to a threshold value of unidirectional signal to actuate the start of whatever predetermined time delay is provided in the operation of the protective relay device. If the instantaneous alternating current in the circuit being protected decreases to a level lower than that which corresponds to the threshold value of the level detecting circuit after a time delay is started but before the end of the predetermined time delay provided, it is desirable that the level detecting circuit reset the operating condition of the overall protective device to the beginning of the time delay provided within a relatively short time. Where a filtered, unidirectional signal is applied to the input of the level detecting circuit, the reset of the protective device may be slowed down depending upon the degree of filtering provided or the output of the level detecting circuit may be chopped in form. It is therefore desirable to provide an improved leveled detecting circuit of the type described which will overcome the disadvantages of known level detecting circuits of the type described as well as provide other advantages.

Summary of the Invention In accordance with the invention, an overcurrent protective relay of the time delay type is provided in which an unfiltered, unidirectional output signal is derived from the alternating current in the circuit being protected and is applied to the input of a level detecting means which provides an output to actuate the start of a predetermined time delay provided in the operation of the overall protective device when the instantaneous current in the circuit being protected increases above a threshold value. If the instantaneous current should exceed the threshold value to start the predetermined time delay and then decrease below the threshold value before the end of the predetermined time delay the level detecting means includes a timing circuit which delays the resetting of the protective device by the level detecting means to the beginning of the predetermined time delay for a predetermined time interval which may be slightly longer than one half cycle of the alternating current in the circuit which is being protected.

It is therefore an object of this invention to provide an improved overcurrent protective relay device of the time delay type including a level detecting circuit which responds substantially instantaneously to a predetermined level of alternating current in a circuit being protected to provide an effective output and which relatively rapidly resets the protective device when the instantaneous current level decreases below the predetermined value after a predetermined time interval.

Brief Description of the Drawings Other objects of the invention will be apparent from the following detailed description taken in conjunction with the accompanying drawings in which:

FIG. I is a schematic diagram, partly in block form, of an overcurrent protective relay device of the time delay type embodying the invention and associated with an electrical system or circuit;

FIG. 2 is a detailed schematic diagram of a portion of the protective device which is shown in block form in FIG. 1-,

FIG. 3 is a detailed schematic diagram of an optional portion of the protective device which is shown in block form in FIG. 1; and

FIG. 4 is a set of waveforms or graphs illustrating the operation of a portion ofthe protective device shown in FIG. I.

Description of the Preferred Embodiments Referring now to the drawings and FIG. I in particular, there is illustrated an overcurrent protective relay device associated with the line conductors L1, L2 and L3 of an electrical power system or circuit to be protected. The electrical system may be of any desired type such as a single-phase system or a polyphase system. It will be assumed for purposes of the present description that the electrical system is a three phase alternating current system represented by the line conductors LI, L2 and L3 and designed for operation at a frequency of 60 cycles per second.

A circuit breaker CE is provided for segregating or isolating portions of the electrical system under certain abnormal or fault conditions, such as an overcurrent condition. The circuit breaker CB includes a plurality of separable line contacts BC], BC2 and BC! which are closed when the circuit breaker is closed and which are opened when the circuit breaker is opened. The circuit breaker CB also includes a trip coil 36 which when energized while the circuit breaker is closed results in a tripping or opening operation of the circuit breaker CB. As illustrated diagrammatically in FIG. I, energization of the trip coil 36 may actuate an operating member 32 to release a latch member 38 to thereby actuate an opening operation of the line contacts BCI, BC2 and 8C3 under the influence of a suitable operating means, such as the spring 34, which may be operatively connected to said line contacts.

In general, the protective device shown in FIG. 1 is arranged to respond to the highest of the line currents which flow in the conductors LI, L2 and L3 to energize the trip coil 36 and to actuate the tripping of the circuit breaker CB after a time delay which is initiated when the highest of the line currents in the conductors LI, L2 and L3 exceeds a predetermined value and which varies substantially inversely with the square of the highest of the line currents in said conductors for a predetermined range of overcurrents in said conductors. Where desired, the protective device shown in FIG. 1 may also respond to the highest of the line currents in the line conductors L1, L2 and L3 to energize the trip coil 36 and to actuate the tripping of the circuit breaker CB in a substantially instantaneous manner without any intentional time delay when the highest of the line currents in said conductors exceeds a predetermined value or to energize the trip coil 36 and to actuate the tripping of the circuit breaker CB after a substantially fixed or predetermined time delay when the highest of the line currents in said conductors exceeds a predetermined value. In addition, where required, the protective device shown in FIG. I may respond to a predetermined ground current in the electrical system which includes the line conductors L1, L2 and L3 to energize the trip coil 36 and to actuate the tripping of the circuit breaker CB after a substantially fixed or predetermined time delay when the ground current exceeds a predetermined value which initiates the start of the substantially fixed or predetermined time delay.

In order to obtain a plurality of output currents which are directly proportional to the line currents in the line conductors L1, L2 and L3, a plurality of current transformers or sensors CTl, CT2 and CT3 are provided as shown in FIG. 1 with the primary windings of said current transformers being energized in accordance with the line currents in the line conduc tors L1, L2 and L3 respectively. The secondary windings of the current transformers CT1, CT2, CT3 are wye connected between the neutral terminal or conductor NT1 and the respective output terminal 52, 62 and 72. ln order to further step down the output currents of the current transformer CTl, GT2 and CT3, the intermediate transformers T1, T2 and T3 which may be of the saturating type are connected between the secondary windings of said current transformers and the input terminals of the power supply input circuit 100 of the protective device shown in FIG. 1. More specifically, the primary windings of the transformers T1, T2 and T3 are wye connected between the output terminals 52, 62 and 72, respec tively, of the current transformers CT1, CT2 and CT3 respectively, and the neutral terminal NT2 with the neutral terminal NT2 being connected to the neutral terminal NTl of said current transformers through the primary winding of a ground current transformer T4 where ground current tripping protection is desired. Where ground current tripping protection is not required, the neutral terminal NT2 at the terminal 44 of the primary winding of the ground current transformer T4 may be directly connected to the neutral terminal NT! of the current transformers CT] CT2 and CT3. The secondary windings of the intermediate transformers T1, T2 and T3 are connected to the input terminals 112 and 114, 122 and 124, and 132 and 134, respectively, of the power supply input circuit 100 of the protective device shown in FIG. 1 to provide three output currents which, in turn, are directly proportional to the line currents in the line conductors L1, L2 and L3 of the electrical system, as illustrated.

In order to rectify the alternating current outputs of the transformers T1, T2 and T3, the power supply input circuit 100 of the protective device shown in FIG. 1 includes a plurality of full wave rectifiers 22, 24 and 26, respectively as illustrated in FIG. 2 of the drawings. As shown in FIG. 2, the input terminals of the full wave rectifier 22 are connected to the terminals 112 and 114 which, in turn, are connected across the secondary winding of the transformer T1. Similarly, the input terminals of the full wave rectifiers 24 and 26 at the terminals 122 and 124 and 132 and 134, respectively, are connected across the secondary windings of the transformers T2 and T3, respectively.

Power Supply Input Circuit 100 In order to develop a plurality of unidirectional voltages which correspond to and are directly proportional to the line currents in the conductors L1, L2 and L3, the power supply input circuit 100 of the protective device includes a plurality of resistors R1, R2 and R3 whose upper ends are connected to the positive output terminals of the full wave rectifiers 22, 24 and 26, respectively. The lower ends of the resistors R1, R2 and R3 are electrically connected together at the conductor P1. One or more filter capacitors, as indicated at C13 in FIG. 2, is connected between the conductor P1 and the negative output terminals of the full wave rectifiers 22, 24, 26 which are electrically connected together to a common terminal, as indicated at the conductor N1. In order to provide a plurality of regulated, filtered unidirectional voltages for the balance of the protective device shown in F168. 1 and 2, a series circuit is connected electrically in parallel with the capacitor C13 between the conductor P1 and the common conductor N1 which includes the forward connected diode D23, a first reversely poled Zener diode Z1, a second reversely poled Zener diode Z2 and a forward connected diode D25.

When the power supply input circuit 100, is initially energized from the current transformers CTl, CT2 and CT3 and the associated transformers T1, T2, T3, the three output currents from the full wave rectifiers 22, 24 and 26 flow through the resistors R1, R2 and R3, respectively, to develop three separate unidirectional voltages which are directly proportional to the line currents in the conductors L1, L2 and L3, respectively and to charge the capacitor C13. The voltages across the capacitor C 13 increases as the capacitor is charged from the full wave rectifiers 22, 24 and 26 until the voltage across the capacitor C13 is sufficient to cause the Zener diodes Z1 and Z2 to break down and limit the voltage across the capacitor C13 to substantially a predetermined value which is equal to the total of the forward voltage drops across the diodes D23 and D25 and the reverse breakdown voltages across the Zener diodes Z1 and Z2. The regulated and filtered voltage across the capacitor C13 which is available between the conductors P1 and N1 may, for example, be of the order of 33 volts while the voltage available between the conductor P2 and the common conductor N1 will be less than the voltage between the conductors PI and N1 by the forward voltage drop across one or more diodes, as indicated by the diode D23. Similarly, the regulated voltage available between the conductor P3 and the common conductor N1 will be less than the voltage between the conductors P1 and N1 by the forward voltage drop across the diode D23 and the reverse breakdown voltage across the Zener diode Z1. It is to be noted that after the Zener diodes Z1 and 22 break down during the initial charging of the capacitor C13, the three unidirectional output currents from the full wave rectifiers 22, 24 and 26 will fiow from the positive terminals of said rectifiers through the respective resistors R1, R2 and R3 to the conductor P1 and then through the series circuit which includes the diode D23, the Zener diodes Z1 and Z2 and the diode 25 to the common conductor N1 which is connected to the negative output terminals of the rectifiers 22, 24 and 26.

In order to obtain a first unidirectional voltage which varies only with the highest of the three unidirectional voltages across the resistors R1, R2, R3 and, in turn, only with the highest of the line currents in the conductors L1, L2 and L3, the power supply input circuit includes a first auctioneering circuit which comprises the diodes D17, D18 and D19. The diodes D17, D18 and D19 are forward connected between the upper ends of the resistors R1, R2 and R3, respectively, at the positive output terminals of the rectifiers 22, 24 and 26, respectively, and a common variable voltage output conductor or bus V1, as shown in FIG. 2. The unidirectional output voltage of the first auctioneering circuit 110 which is available or appears between the conductor V1 and the conductor Pl will be equal to the highest voltage across resistors R1, R2 and R3 less the forward voltage drop across one of the diodes D17, D18 and D19 since if the unidirectional voltage across one of said resistors exceeds the unidirectional voltages across the other two of said resistors, two of the three diodes D17, D18 and D19 will be blocked or reversed biased by the highest unidirectional voltage which is present between the conductors V1 and P1. It is important to note that the unidirectional output voltage which appears between the conductors V1 and P1 is unfiltered for reasons which will be explained hereinafter.

In order to obtain a second unidirectional output voltage which varies only with the highest of the three unidirectional voltages across the resistors R1, R2 and R3 and, in turn with only the highest of the line currents in the conductors L1, L2 and L3, the power supply input circuit 100 includes a second auctioneering circuit which includes the diodes D20, D21 and D22. Similarly to the diodes of the first auctioneering circuit 100, the diodes D20, D21 and D22 are connected to the upper ends of the resistors R1, R2 and R3, respectively, at the positive output terminals of the rectifiers 22, 24 and 26, respectively, and a common variable voltage output conductor V2 which forms part of the long time delay tripping circuit 200, as shown in FIG. 2. The unidirectional output voltage of the second auctioneering circuit 120 is available between the conductors V2 and the conductor P1 and is equal to the highest of the three unidirectional output voltages across the resistors R1, R2 and R3 less the forward voltage drop across one of the diodes D20, D21 and D22. The unidirectional output voltage of the second auctioneering circuit 120 is filtered by the capacitor C1 which is connected between the conductor V2 and the conductor P1. The second auctioneering circuit 120 operates similarly to the first auctioneering circuit 110 in that when one of the three unidirectional voltages across the resistors R1, R2, R3 exceeds the other two unidirectional voltages, two of the forward connected diodes D20, D21 and D22 will be blocked or reversed biased.

In order to prevent the operation of the protective device shown in FIG, 1, prior to the time that the capacitor C13, which may include one or more energy storing capacitors in a particular application, is fully charged or in the event that the capacitor C13 should not be fully charged during the operation of the protective device shown in FIG. 1, the power supply input circuit 100 includes the control means or circuit 150 which comprises the NPN transistors 01 and 02, as shown in FIG. 2V in general, the control means 150 of the power supply input circuit 100 is provided to insure that the capacitor C13 has acquired sufficient charge or stored energy to adequately energize the trip coil 36 of the circuit breaker CB when called upon to do so during the operation of the protective device shown in H6. 1, as will be explained in greater detail hereinafter. More specifically, the control means 150 of the power supply input circuit 100 includes a voltage dividing network which comprises the resistors R5 and R6 connected in series with one another, the series circuit being electrically connected in parallel with the diode D25 between the anode of the diode D25 and the common or negative conductor N1. When the capacitor C13 is fully charged and the Zencr diodes Z1 and Z2 break down, the diode D25 limits the voltage across the series circuit which includes the resistors R5 and R6 to the forward voltage drop of the diode D25. In order to apply a drive current to the base of the transistor ()1 when the capacitor C13 is fully or adequately charged, the base of the transistor 01 is connected to the junction point between the resistors R5 and R6, while the emitter of the transistor 01 is connected to the common conductor N1. The collector of the transistor T1 is connected to the conductor P1 through a collector load resistor R4 and is also directly connected or cou pled to the base of the transistor 02. The emitter of the transistor ()2 is also directly connected to the common conductor N1, while the collector of the transistor 02 is connected to the collector of the transistor 015 which forms part of the output circuit 400, as shown in FIG. 2, through a conductor 262 and a diode D48 which is a normally block or reversed biased, isolating diode, whose purpose will be explained in more detail hereinafter.

1n the operation of the control means 150, prior to the time that the charge on the capacitor C13 and the corresponding voltage thereacross is sufficient to break down the Zencr diodes Z1 and Z2 in the reverse direction or whenever the charge on the capacitor C13 and the corresponding voltage thereacross is insufficient to break down said Zencr diodes during the operation of the overall protective device shown in FIG. 1, the current flowing in the base-emitter circuit of the transistor 01 will be insufficient to actuate the transistor O1 to a saturated condition and the transistor Q1 will therefore be substantially nonconducting or cutoff. Whenever the transistor ()1 is substantially nonconducting or cutoff and a unidirectional output voltage is present at the conductor P1, current will flow from the conductor P1 to the conductor N1 through the resistor R4 and the base-emitter circuit of the transistor 02 to actuate the transistor 02 to a saturated condition in which the voltage drop across the collector-emitter circuit of the transistor Q2 will be relatively negligible and the voltage or potential at the conductor 262 will be very close to the potential at the common conductor N1. Whenever the potential at the conductor 262 is held at a value which is very close to the potential at the common conductor N1, the diode D48 in the output circuit 400 of the protective device will be unblocked or forward biased to thereby prevent the operation of the output circuit 400 of the protective device shown in FIG. 1, as will be explained in detail hereinafter.

1n the operation of the control means 150, after the capacitor C13 is fully or adequately charged sufficiently to break down the Zencr diodes Z1 and Z2 or whenever the charge on the capacitor C13 and the corresponding voltage thereacross is sufficient to break down said Zencr diodes in the reverse direction, current will flow through the series circuit which includes the diode D23, the Zencr diodes Z1 and Z2, the resistor R5, and the base-emitter of the transistor Q1 which is sufficicnt to actuate the transistor 01 to a saturated condition in which the current flowing in the collector-emitter circuit of the transistor ()1 is limited only by value of the resistor R4 which is connected in series with the collector ofthe transistor Q1 and the voltage between the conductor PI and the conduc tor N1. When the transistor O1 is actuated to a saturated condition as just described, the potential at the base of the transistor 02 will change to a potential which is very close to the potential at the common conductor N1 and the current flow in the base-emitter circuit of the transistor 02 will be reduced to a value less than that necessary to maintain the transistor 02 in a saturated condition and the transistor 02 will therefore be actuated to a substantially nonconducting or cutoff condition. When the transistor 02 is actuated to a substantially nonconducting or cutoff condition, the potential at the conductor 262 with respect to the potential at the conductor N1 will be raised sufficiently to block or reverse bias the diode D48 and the output circuit 400 of the protected device shown in FIG. 1 will be permitted to operate in normal fashion, since the capacitor C13 will be assured a sufficient charge and corresponding voltage thereacross to energize the trip coil 36 of the circuit breaker CB when called upon to do so during the operation of the protective device as shown in FIG. I. It is to be noted that the value of the resistor R6 which forms part of the control means 150 may be selected so as to determine the minimum current in the base-emitter circuit of the transistor Q1 which is necessary to actuate the transistor Q] from a substantially nonconducting or cutoff condition to a saturated condition to thereby decrease the sensitivity of the control means 150, as desired, in a particular application.

Long Time Delay Tripping Circuit 200 In general, the long time delay tripping circuit 200 is connected between the power supply input circuit and the output or level detecting circuit 400 of the protective device shown in FIG. 1 to respond to the highest of the unidirectional voltages developed across the resistors R1, R2 and R3 which appear at the conductors V1 and V2 to actuate the output circuit 400 to energize the trip coil 36 of the circuit breaker CB and trip said circuit breaker open whenever the highest of the line currents flowing in the line conductors L1, L2 and L3 exceeds a predetermined value after a time delay which varies substantially inversely with the square of the ovcrcurrent over a predetermined range of overcurrcnts and which is initiated when the highest of the line currents in said conductors exceeds the predetermined or threshold value, More specifically, the long time delay tripping circuit 200 includes the first and second substantially constant current sources or circuits 210 and 220 respectively, which are connected to the variable voltage output conductor V2 of the second auctioneering circuit for converting the highest of the unidirectional voltages across the resistors R1, R2 and R3 to first and second substantially predetermined unidirectional output currents which are maintained at substantially constant values for a particular value of the highest unidirectional voltage across said resistors independently of changes in the loads connected at the outputs of said current circuits, The unidirectional output currents of the current circuits 210 and 220 which vary in a substantially linear manner with and are directly proportional to the highest of the unidirectional voltages across the resistors R1, R2 and R3 and, in turn, vary in a substantially linear manner and are directly proportional to the highest of the line currents in the conductors L1, L2 and L3 are then applied to a pulse generating circuit 230 for producing output pulses of unidirectional current whose frequency of repetition rate and magnitude or amplitude both vary in a substantially linear manner with the highest of the line currents in the conductors L1, L2 and L3, with each of said pulses having a substantially predetermined width or duration. The output pulses of unidirectional current from the pulse generating circuit 230 are applied to a timing capacitor or integrating capacitor C4 to cumulatively charge the capacitor C4 when permitted to do so by a level detecting circuit 260 which is connected to the variable voltage conductor V1 to permit the charging of the capacitor C4 when the highest of the line currents in the conductors L1, L2 and L3 increases to substantially a predetermined or threshold overcurrent value. When the pulse generating circuit 230 is permitted to charge the capacitor C4 cumulatively as permitted by the operation of the level detecting circuit 260, the charge across the capacitor C4 increases gradually to a predetermined or threshold value after a time delay which varies substantially inversely with the square of the highest line current in the conductors L1, L2 and L3 to actuate the operation of the output circuit 400 of the protective device shown in FIG. 1 to energize the trip coil 36 of the circuit breaker CB. In order to periodically increase the effective voltage across the timing capacitor C4 for reasons which will be explained hereinafter, the long time delay tripping circuit 200 also includes an auxiliary pulse generating circuit 240 which is responsive to the output pulses of the pulse generat' ing circuit 230 to periodically increase the effective charge and corresponding voltage across the timing or integrating capacitor C4.

More specifically, the first current circuit means 210 is connected to the second auctioneering circuit 120 for converting the highest unidirectional voltage across the resistors R1, R2 and R3 to a first unidirectional output current which is main tained at substantially a predetermined or constant value for a particular value of the highest unidirectional voltage across said resistors and which varies in a substantially linear manner with the highest unidirectional voltage across said resistors. The first current circuit means 210 comprises a PNP transistor 05 and the resistor R9 which is electrically connected in series with the emitter of the transistor 05 between the variable voltage conductor V2 at the upper end of the capacitor C1 and the emitter of the transistor T5. The base of the transistor 05 is connected to the conductor P2 in order that the input voltage of the first circuit means 210 between the conductors V2 and P2 include the forward voltage drop of the diode D23 which may include one or more forward connected diodes in a particular application to thereby compensate the input voltage of the first circuit means 210 for the forward voltage drop across one of the diodes D20, D21 and D22 which is connected between one of the resistors R1, R2 and R3 having the highest unidirectional voltage thereacross and the variable conductor V2 and the forward voltage drop across the baseemitter circuit of the transistor 05. The emitter current of the transistor 05 is therefore equal to the ratio of the highest unidirectional voltage across one of the resistors R1, R2 and R3 to the value of the resistor R9 which is connected in series with the emitter of the transistor Q5. The unidirectional out put current of the first circuit means 210 is available at the collector of the transistor Q5 which is connected to the left side of the capacitor C3 at the terminal 272. In order to maintain the unidirectional output current of the first circuit means 210 at substantially a predetermined or constant value for a particular value of the highest unidirectional voltage across the resistors R1, R2 and R3, the input voltage applied across the series circuit which includes the resistor R9 and the emitter-base circuit of the transistor 05 should be relatively high, such as the order of 10 to 20 times the forward voltage drop across the emitter-base circuit of the transistor 05. In addition, the transistor Q5 should have a relatively high current gain or ratio of emitter current to base current, such as of the order of 100, at the particular level of output current at which the transistor 05 is operating in order that the base current of the transistor 05 be negligible compared with the emitter current and the collector current of the transistor 05 be substantially equal to the emitter current. In the operation of the first circuit means 210, the unidirectional output current at the collector of the transistor 05 is maintained at a substantially predetermined or constant value for a particular value of the highest unidirectional voltage across the resistors R1, R2 and R3 independent of changes in whatever load circuit is connected to the collector of the transistor 05 and the unidirectional output current at the collector of the transistor 05 varies in a substantially linear manner with the highest unidirectional voltage across the resistors R1, R2 and R3 and, in turn, with the highest line current in the conductors L1, L2 and L3.

Similarly, the second current circuit means 220 is connected to the first auctionecring circuit for converting the highest unidirectional voltage across the resistors R1, R2 and R3 to a second unidirectional output current which is maintained at substantially a predetermined or constant value for a particular value of the highest unidirectional voltage across said resistors independent of changes in whatever load circuit is connected to the output of the second current circuit means 220 and which varies in a substantially linear manner with the highest unidirectional voltage across said resistors. The second current circuit means 220 comprises the PNP transistor 06, the resistor R13 which is connected in series with the emitter of the transistor 06 and the rheostat or variable resistance means R38 which is connected in series with the resistor R13 and the emitter of the transistor 216 between the second variable voltage conductor V2 and the emitter of the transistor 06. The base of the transistor O6 is connected to the conductor P2 in order that the input voltage of the second circuit means 220 between the conductor V2 and the conduc tor P2 include the forward voltage drop across the diode D23 to thereby compensate the input voltage of the second circuit means 220 for the forward voltage drop across one of the diodes D20, D21 and D22 which is connected between one of the resistors R1, R2 and R3 having the highest unidirectional voltage thereacross and the variable voltage conductor V2 and the forward voltage drop across the emitter-base circuit of the transistor 06. The emitter current of the transistor 06 is substantially equal to the input voltage of the second circuit means 220 between the conductors V2 and P2 divided by the total resistance of the rheostat R38 and the resistor R13. Since the transistor 06 is selected to have a relatively high current gain or ratio of emitter current to base current, such as of the order of 100, at the particular level of the emitter current at which the transistor 06 is operating. the base current of the transistor ()6 is substantially negligible and the unidirectional output current of the transistor 06 at the collector of the transistor O6 is substantially equal to the emitter current of the transistor ()6. In order that the unidirectional output current of the second circuit means 220 at the collector of the transistor 06 be maintained at substantially a predetermined constant value for a particular value of the highest unidirectional voltage across the resistors R1, R2 and R3, the input voltage applied to the second circuit means 20 between the conductor V2 and the conductor P2 should be relatively large compared with the forward voltage drop of the emitterbase circuit of the transistor Q6. The setting of the rheostat R38 may be adjusted to vary the unidirectional output current of the second circuit means 220 at the collector of the transistor ()6 which corresponds to a particular value of the highest unidirectional voltage across the resistors R1, R2 and R3 and, in turn, with the highest line current in the conductors L1, L2 and L3 It is to be noted that a portion of the input voltage applied to the second current circuit means 220 between the conductor V2 and the conductor P1, which is the same input voltage applied to the input of the first circuit means 210, if filtered by the capacitor C1. it is also to be noted that similar to the first current circuit means 210, the unidirectional output current of the second circuit means 220 which is available at the collector of the transistor 06 also va ries in a substantially linear manner with the highest unidirectional voltage across the resistors R1, R2 and R3 and, in turn, with the highest line current in the conductors Ll, L2 and L3 respectively. The collector of the transistor 06 of the second current circuit means 220 is connected to the upper side of the timing or integrating capacitor C4 through the diode D30 and cumulatively charges the timing capacitor C4 when permitted to do so by the operation of other portions of the overall protective device shown in FIG. 1 as explained hereinafter.

In order to control the application of the unidirectional output current from the second circuit means 220 to the timing capacitor C4 in the form of periodic pulses of current whose frequency and magnitude both vary in a substantially linear manner or are directly proportional to the highest line current in the conductors LI, L2 and L3 and whose width remains at a substantially predetermined duration when permitted to do so by the level detecting circuit 60 of the long time delay tripping circuit 200 as will be explained hereinafter, the pulse generating circuit 230 is connected to the first and second current circuit means 210 and 220, respectively, and to the positive conductors PI and P3 which supply regulated and filtered unidirectional voltages to the pulse generating circuit 230 which is described in more detail in copending application Ser. No. 765,584 filed concurrently herewith by .I. D. Watson, F. T. Thompson and F. 0. Johnson which is assigned to the same assignee as the present application.

More specifically, the pulse generating circuit 230 comprises a breakover device, such as the unijunction transistor or double base diode 04, the NPN transistor ()7 and the energy storing capacitor C3.

It is to be noted that the unidirectional, regulated potential at the conductor Pl may, for example, be approximately 33 volts which is positive with respect to the potential at the common or negative conductor N1, while the unidirectional regulated potential at the conductor P3 may be approximately one-half the voltage at the conductor PI or may be, for example, at a voltage of approximately 16.5 volts which is positive with respect to the potential at the common conductor Nl. The lower base of the unijunction transistor O4 is connected directly to the common conductor N1 while the upper base of the transistor 04 is connected to the conductor P3 through the resistor R10 to apply a substantially predetermined interbase potential to the transistor 04 prior to the breakover ol' the transistor ()4. The emitter of the transistor 04 is connected to the left side of the capacitor C3 at the terminal 272 which, in turn, is connected to the first circuit means 210 at the collector of the transistor 05. The right side of the capacitor C3 at the terminal 282 is connected to the conductor P] through the resistor R11 and to the base of the transistor 07 through the diode D28. The base of the transistor 07 is connected to the common conductor Nl through the resistor R12 which acts as a shunt resistor which is electrically connected in parallel with the base-emitter circuit of the transistor 07 to decrease the sensitivity of the transistor 07 and to establish the minimum current in the base-emitter circuit of the transistor 07 necessary to actuate the transistor 07 to a saturated condition. The emitter of the transistor ()7 is directly connected to the common conductor NI, while the collector of the transistor 07 is connected to the collector of the transistor Q6 which forms part of the second current circuit means 220 and is also connected to the upper side of the timing or integrating capacitor C4 through the diode D30.

In general, the pulse generating circuit 230 operates as a relaxation oscillator or sawtooth voltage generator which de pends upon the operating characteristics of the particular breakover device which is employed as part of the circuit 230 and which, as illustrated, is the unijunction transistor 04. The typical operating characteristics of a suitable breakover device such as the unijunction transistor 04, a four-layer diode, a transistor breakover circuit or other suitable circuit is such that when the voltage or potential applied between the emitter and the lower base of the transistor 04 exceeds substantially a predetermined fraction or percentage of the potential applied between the upper base and the lower base of the transistor 04 which may be referred to as the peak point voltage of the transistor 04, the resistance or impedance between the emitter and the lower base of the transistor 04 will decrease suddenly until the voltage between the emitter and the lower base of the transistor 04 decreases to a relatively much lower voltage which may be referred to as the valley voltage of the transistor 04 as disclosed in greater detail in the last-mentioned copending application.

In considering the detailed operation of the pulse generating circuit 230, it will be assumed initially that the voltage applied between the emitter and the lower base of the transistor 04 is less than the peak point voltage necessary to cause the transistor 04 to break over and that the transistor 07 is being held in a substantially saturated condition by the base drive current which flows from the positive conductor Pl through the resistor R11, the forward connected diode D28 and the basc-emitter circuit of the transistor 07 to the common conductor N1. It is to be noted that during the assumed initial operating condition, the right side of the capacitor C3 at the terminal 282 will be held or clamped at a positive potential with respect to the common conductor NI which is equal to the sum of the forward voltage drops across the diode D28 and the base-emitter circuit of the transistor 07. It is also to be noted that the unidirectional output current of the second current circuit means 220 at the collector of the transistor 06 which is maintained at substantially a predetermined or constant value for a particular value of the highest unidirectional voltage cross resistors R1, R2 and R3 will be diverted away from or by passed around the timing capacitor C4 through the collector-emitter path of the transistor 07 to the common conductor NI, as long as the diode D28 is forward biased and the transistor 07 is held in a saturated condition.

In the operation of the pulse generating circuit 230, assuming that the magnitude of the highest unidirectional voltage across the resistors RI, R2 and R3 which is directly proportional to the highest line current flowing in the conductors L1, L2 and L3 remains at a particular value, the unidirectional output current from the first current circuit means 210 which appears at the collector of the transistor 05 will be maintained at a substantially predetermined or constant value and will be applied to the left side of the energy storing capacitor C3 at the terminal 272 to gradually charge the capacitor C3 in a substantially linear manner until the voltage at the terminal 272 exceeds the peak point voltage of the unijunction transistor 04. When the voltage at the terminal 272 exceeds the peak point voltage of the transistor 04, the transistor 04 breaks over and the voltage at the terminal 272 at the left side of the capacitor C3 suddenly decreases from the peak point voltage to the valley voltage of the transistor 04 with a resulting voltage change at the terminal 272 which is equal to the difference between the peak point voltage and the valley voltage of the transistor 04. For example, the potential or voltage of terminal 272 may decrease suddenly from a voltage of approximately I0 volts which is positive with respect to the common conductor N1 to a valley voltage of approximately 3 volts which is positive with respect to the common conductor N1 when the transistor 04 breaks over during the charging of the capacitor C3. It is to be noted that prior to the breakover of the transistor Q4, the voltage across the capacitor C3 will increase due to the charging current from the first current circuit means 210 to approximately the voltage at the terminal 272 which may, for example, be approximately I0 volts which is positive with respect to the common conductor N1 less the two forward voltage drops across the diode D28 and the baseemitter circuit of the transistor 07 or the net voltage across the capacitor C3 may be approximately 9.4 volts prior to the breakover of the transistor ()4. When the transistor 04 breaks over and the voltage at the terminal 272 suddenly decreases to the valley voltage of the transistor 04, the voltage at the terminal 282 at the right side of the capacitor C3 will change correspondingly in a negative direction substantially instantaneously since there is no low resistance discharge path provided for the capacitor C3.

The voltage at the terminal 282 at the right side of the capacitor C3 will for example, change in a negative direction to a value which is equal for example to a voltage of three volts which is positive with respect to the common conductor NI less 9.4 volts which is the approximate voltage across the capacitor C3, for example, giving a voltage which is approiu mately equal to 6.4 volts which is instantaneously negative with respect to the common conductor Nl. The diode D28 will then be reverse biased or blocked and the transistor 07 will be actuated to a substantially cutoff or nonconducting condition since the base drive current will be effectively removed from the base-emitter circuit of the transistor 07.

When the voltage at the right side of the capacitor C3 changes in a negative direction to a voltage value which is negative with respect to the voltage at the common conductor N1, the right side of the capacitor C3 will then be charged from the positive conductor Pl through the resistor R" with the charging current flowing through the emitter and the lower base of the transistor ()4 to the common conductor N]. The voltage at the terminal 282 will gradually increase in a positive direction until the diode D28 is forward biased and the current in the base-emitter circuit of the transistor 07 ac tuates the transistor 07 to substantially a saturated condition. it is to be noted that the transistor 04 will be held in a substantially conducting condition in the circuit which includes the emitter and the lower base of the transistor 04 by the charging current which flows from the positive conductor P] to the right side of the capacitor C3 until the diode D28 becomes forward biased and the transistor ()7 is actuated to substantially a saturated condition. When the transistor 04 is no longer held in a substantially conducting condition in the circuit which includes the emitter and the lower base the transistor ()4 will then be reset to a substantially nonconducting condition in the emitter-lower base circuit. The current from the collector of the transistor of the first current cir cuit means 210 is not sufficient to maintain the transistor ()4 in a substantially conducting condition by itself because of the resistor R9 which is connected in series with the emitter of the transistor 05. The time interval or period required to charge the right side of capacitor C3 at the terminal 282 following the breakover of the transistor ()4 is determined by the time con stant of the resistor-capacitor combination which includes the capacitor C3 and the resistor R11 which is charged from the voltage between the positive conductor P1 and the common conductor N 1.

While the transistor ()7 is rendered substantially nonconducting or cutoff for substantially a predetermined time inter val or period following the breakover of the transistor ()4, a pulse of the unidirectional output current at the collector of the transistor 06 of the second current circuit means 220 is diverted from the collector-emitter path of the transistor 07 to a current path which includes the diode D30 and is applied to charge the timing capacitor C4 when permitted to do so by the operation of the level detecting means 260 as will be explained hereinafter. The pulses of current which are periodi cally available from the collector of the transistor 06 and which are diverted from the emitter-collector circuit of the transistor 07 to the current path which includes the diode D30 will have a magnitude or amplitude which will vary in a substantially linear manner with the highest of the unidirectional voltages across the resistors R1, R2 and R3 and, in turn, with the highest of the line currents which flow in the conductors L1, L2 and L3, respectively. Since the time required to charge the capacitor C3 and periodically breakover the transistor 04 will also vary in a substantially linear manner and be directly proportional to the output unidirectional current of the first current circuit means 210 at the collector of the transistor 05, the frequency or repetition rate of the output current pulses from the pulse generating circuit 230 will also vary a substantially linear manner with the highest of the unidirectional voltages across the resistors Rl, R2 and R3 and, in turn, with the highest line current which flows in the conductors Ll, L2 and L3. It is to be noted that the periodic pulses of output current which are applied from the collector of the transistor 06 to the current path which includes the diode D30 occur at the end of each sawtooth voltage waveform which is produced or generated by the pulse generating circuit 230 and that the duration of the pulses is determined by the time required to charge the right side of the capacitor C3 from the regulated voltage at the positive conductor Pl through the resistor R11 to sufficiently forward bias the diode D2! and to actuate the transistor 07 to substantially a saturated condition following the breakover of the transistor 04. The duration or time width of the periodic output pulses of current from the pulse generating circuit 230 will therefore remain substantially constant or at a predetermined value since the time width of said pulses will be substantially inde pendent of variations in the highest line current which flows in the conductors L1, L2 and L3 and the corresponding highest unidirectional voltage across the resistors R1, R2 and R3, respectively. When the pulse generating circuit 230 is permitted to charge the timing or integrating capacitor C4 by the operation of the level detecting means 260, as will be explained hereinafter, the voltage across the capacitor C4 will vary in a substantially linear manner with both the frequency and the magnitude or amplitude of the pulses of output current from the collector of the transistor 06 which flows through the diode D30 as just described. The voltage across the timing capacitor C4 therefore will vary substantially with the square of the highest unidirectional voltage across the resistors R1, R2 and R3 and, in turn, with substantially the square of the highest line current flowing in the conductors Ll, L2 and L3.

In summary, the pulse generating circuit 230, as disclosed in greater detail in the copending application previously mentioned, operates to produce periodic pulses of output current to charge the timing capacitor C4 when permitted to do so by the operation of the level detecting circuit 260 with both the frequency or repetition rate and the magnitude or amplitude of the pulses of output current from the pulse generating circuit 230 varying in a substantially linear manner with the highest line current flowing in the conductors L1, L2 and L3 and with the time duration or the width of said output pulses being maintained at substantially a predetermined or constant value by the operation of the pulse generating circuit 230, as just described. As described in copending application Ser, No, 765,584 previously mentioned the operating characteristics of the pulse generating circuit 230 are such as to substantially compensate for changes in the value of the capacitor C3 and for changes in the operating characteristics in the transistor 04 due to changes in these components with changes in environmental conditions, such as temperature.

in accordance with the invention, the level detecting circuit or means 260 of the long time delay tripping circuit 200 is connected to the first auctioneering circuit and to the timing or integrating capacitor C4 to respond to the highest instantaneous unidirectional voltage across the resistors R1, R2 and R3 and, in turn, to the highest of the instantaneous line currents flowing in the conductors L1. L2 and L3 to permit the pulse generating circuit 230 to start charging the timing capacitor C4 when the highest instantaneous line current in the conductors L1, L2 and L3 exceeds a predetermined or threshold value and to permit the pulse generating circuit 230 to continue charging the timing capacitor C4 depending upon changes in the highest instantaneous line current flowing in the conductors L1, L2 and L3.

The level detecting circuit 260 includes the PNP transistors 08 and 09 which are connected to control the conducting state of a control means 270 which comprises a PNP transistor Qll) which is connected to normally divert the output pulses of current from the pulse generating circuit 230 away from or around the timing capacitor C4 to the common or negative conductor Nl.

More specifically, the input circuit of the level detecting means 260 comprises a voltage dividing network which includes the rheostat or variable resistance means R39 the resistor R14 and the resistor R15 which are connected electrically in series with one another, the series circuit being connected between the variable output conductor V1 of the first auctioneering circuit 110 and the positive conductor P3 which provides one of the regulated, unidirectional output voltages from the power supply input circuit 100. It is important to note that the unidirectional voltage at the variable voltage conductor V1 varies substantially instantaneously with the highest of the unidirectional voltages across the resistors R1, R2 and R3, since the voltage at the conductor V1 is not fil tered by the capacitor C1 as is the output voltage at the variable voltage conductor V2. The base of the transistor 08 is connected to the junction point between the resistors R14 and R15, while the emitter of the transistor 08 is directly connected to the positive conductor P1. The diode D29 is connected between the base and emitter of the transistor 08 to limit the inverse voltage which is applied between the emitter and the base of the transistor 08 when the transistor 08 is not substantially nonconducting or cutoff and to prevent the baseemitter circuit of the transistor 08 from breaking down under the inverse voltage which might otherwise be applied to the base-emitter circuit of the transistor 08. The collector of the transistor 08 is connected to the common conductor N1 through the collector load resistor R16. The transistor 09 is directly coupled to the output of the transistor ()8 since the base of the transistor 09 is connected to the collector of the transistor 08, while the emitter of the transistor 09 is directly connected to the positive conductor P1. The collector of the transistor 09 is connected to the common conductor N1 through the collector load resistor R17. The capacitor C is connected between the emitter and the collector of the transistor 09 to form a timing circuit with the resistor R17 which delays the resetting of the level detecting circuit, when the magnitude of the highest line current flowing in the conductors L1, L2 and L3 decreases below a predetermined or threshold value after exceeding the predetermined or threshold value, as will be explained hereinafter. The transistor Q which forms the control means 270 is directly coupled to the transistor 09 with the collector of the transistor 09 being directly connected to the base of the transistor 010. The collector of the transistor 010 is directly connected to the common conductor N1, while the emitter of the transistor 010 is connected to the positive conductor P3 through a series circuit which includes the forward connected diode'D35, the forward connected diode D46, and the resistor R35 of the output circuit 400 and the forward connected diode D45 of the output circuit 400. The resistor R18 is connected between the base and emitter of the transistor Q10 to decrease the sensitivity which might otherwise result in the operation of the transistor Q10 and to establish the minimum base-emitter current necessary to actuate the transistor 010 to substantially a saturated condition.

In the operation of the level detecting circuit 260 it is important to note that since the output of the first auctioneering circuit 110 at the variable voltage conductor V1 which forms the input of the level detecting circuit 260 is unfiltered, the input of the level detecting circuit 260 as illustrated in FIG. 4A and as indicated at V comprises a series of unidirectional output pulses as indicated at 810 and 820 each of which has substantially the configuration as the corresponding one-half cycle of the highest line current flowing in the line conductors L1, L2 and L3. in other words, the magnitude of the unidirectional voltage pulses applied at the input of the level detecting circuit 260 at the variable voltage conductor V1 varies substantially instantaneously with the corresponding highest line current flowing in the conductors L1, L2 and L3. It is also to be noted that the unidirectional voltage pulses applied at the input of the level detecting circuit 260 correspond only to the highest of the unidirectional voltages developed across the resistors R1, R2 and R3 due to the operation of the first auctioneering circuit 110, as previously explained.

When the highest instantaneous line current flowing in the conductors L1, L2 and L3 is less than substantially a predetermined value and the corresponding highest instantaneous unidirectional voltage across the resistors R1, R2 and R3, as indicated at 810 in FIG. 4A, is less than a substantially predetermined or threshold voltage, as indicated at V in FIG. 4A, the transistor 08 of the level detecting circuit 260 is actuated to substantially a saturated condition since the emitterbase circuit of the transistor 08 is forward biased and a base drive current flows from the positive conductor P1 through the emitter-base circuit of the transistor 08 and the resistor R15 to the positive conductor P3. When the transistor 08 is in a normally saturated condition, the voltage drop across the resistor R15 which is connected between the base of the transistor 08 and the conductor P3 is equal to the voltage difference between the conductors P1 and P3 less the forward voltage drop across the emitter-base circuit of the transistor 08. For example, if the unidirectional voltage at the conductor P1 is approximately 33 volts which is positive with respect to the common conductor N1 and the voltage at the conductor P3 is approximately 16.5 volts which is positive with respect to the common conductor N1, the voltage across the resistor R15 will be approximately 16.5 volts less the forward voltage drop across the emitter-base circuit of the transistor ()8 or approximately 16 volts. In other words, when the transistor O8 is in a normally saturated condition, the voltage at the base of the transistor ()8 will differ from the voltage at the positive conductor Pl only by the forward voltage drop of the emitter-base circuit of the transistor 08. The sum of the instantaneous voltage drops across the rheostat R39 and the resistor R14 will be substantially equal to the highest of the instantaneous unidirectional voltages across the resistors R1, R2 and R3, since the forward voltage drop across one of the diodes D17, D18 or D19 of the first auctioneering circuit will substantially compensate or the forward voltage drop across the emitter-base circuit of the transistor 08 and will also assist in temperature compensating the operation of the level detecting circuit 260 for variations which may occur in the forward voltage drop across the emitter-base circuit of the transistor 08 due to changes in the environmental temperature. Since the sum of the voltage drops across the rheostat R39 and the resistor R14 is substantially equal to the highest of the unidirectional voltages across the resistors R1, R2 and R3, the current flowing through rheostat R39 and the resistor R14 will be equal to the highest unidirectional voltage across said resistors divided by the sum of the resistances of the rheostat R39 and the resistor R14.

As the highest unidirectional voltage across the resistors R1, R2 and R3 increases prior to reaching the predetermined voltage previously mentioned, the current which flows through the rheostat R39 and the resistor R14 increases while the current which flows the emitter-base circuit of the transistor 08 decreases. This is because the voltage across the resistor R15 is constrained to be equal to the voltage difference between the conductors P1 and P3 less the forward voltage drop across the emitter-base circuit of the transistor 08 as long as said transistor remains in a saturated condition, as previously explained.

As long as the transistor 08 remains in a saturated condition, the current which flows in the resistor R16 will be diverted to the emitter-collector circuit of the transistor 08 and the voltage drop across the resistor R16 will be as illustrated at V in FIG. 4B. The voltage drop across the resistor R16 is indicated at 832 in FIG. 6 when the transistor 08 is in a saturated condition. The diverting of the current which flows in the resistor R16 through the emitter-base circuit of the transistor 08 will maintain the transistor 09 in a substantially nonconducting or cutoff condition. As long as the transistor 09 is maintained in a substantially nonconducting or cutoff condition, the current flow through the emitter-collector circuit of the transistor Q9 will be substantially negligible and the voltage drop across the resistor R17 which is illustrated at V in FIG. 4C and which is due, in part, to the emitter-collector current of the transistor 09 will be relatively low, as indicated at 852 in H0. 4C. The voltage at the base of the transistor 010 which is connected to the upper end of the resistor R17 will therefore be at a value, as indicated at 852 in FIG. 4C which is relatively close to the voltage at the common conductor N1 and a base drive current will flow from the positive conductor P3 through the series circuit which includes the diode D45, the resistor R35, the diode D46, the diode D35, the emitter-base circuit of the transistor Q10 and the resistor R17 to the common conductor NI. The transistor 010 will therefore be normally maintained in substantially a saturated condition to thereby provide a low resistance path from the upper side of the timing or integrating capacitor C4 through the forward connected diode D31, the forward connected diode D35 and the emitter-collector circuit of the transistor 010 to the common or negative conductor N1 to thereby prevent the output pulses of current from the pulse generating circuit 230 from cumulatively charging the timing capacitor C4. In other words, the effective output of the level detecting circuit 260 which may be considered to be the voltage at the emitter of the transistor 210 with respect to the common conductor N1 which is illustrated at V,- in FIG. 40 substantially negligible as long as the highest line current flowing in the conductors L1, L2 and L3 remain below a predetermined or threshold value and the transistor Q10 is held in a saturated condition as just described. It is to be noted that in the normal operating condition of the level detecting circuit 260, as long as the highest line current flowing in the conductors L1, L2 and L3 remains below a predetermined or threshold value and the corresponding highest unidirectional voltage across the resistors R1, R2 and R3 remains below a corresponding predetermined voltage value, the transistor 09 will remain in a substantially nonconducting or cutofl' condition and the capacitor C5 which is connected between the emitter and the collector of the transistor ()9 will charge to a voltage which is substantially equal to the voltage difference between the positive conductor P1 and the common conductor N1 less a relatively small voltage drop across the resistor R17.

When the highest line current flowing in the conductors L1, L2 and L3 exceeds or increases to a value above the predetermined or threshold value to which the level detecting circuit 260 responds and the corresponding highest unidirectional instantaneous voltage across the resistors R1, R2 and R3 as indicated at 820 in FIG. 4A exceeds a corresponding predetermined or threshold voltage value, as indicated at V,- in FIG. 4A, the current through the rheostat R39 and the resistor R14 increases while the transistor 08 is still in a saturated condition until the current in the emitter-base circuit of the transistor 08 decreases to an negligible value and the transistor O8 is thereby actuated to a substantially nonconducting or cutofl condition. It is to be noted that the predetermined highest instantaneous line current in the conductors L1, L2 and L3 at which the transistor O8 is actuated to a substantially nonconducting condition may be adjusted by the setting of the rheostat R39. When the transistor O8 is actuated to a substantially nonconducting condition, the current in the emitter-collector path of the transistor 08 decreases to a sub stantially negligible value and the current which flows in the resistor R16 now flows from the positive conductor P1 through the emitter-base circuit of the transistor 09. The voltage drop across the resistor R16 also decreases to a relatively lower value, as indicated at 830 in FIG. 4B. The transistor Q9 then carries saturated current in the emitter-collector circuit of the transistor 09 to increase the voltage drop across the resistor R17, as indicated at 850 in FIG. 4C, with the voltage at the base of the transistor Q increasing to a value which is substantially equal to the voltage at the emitter of the transistor 010 to thereby remove the forward bias from the emitter-base circuit of the transistor Q10 and to actuate the transistor 010 to substantially nonconducting or cutoff condition. When the transistor 010 which forms the control means 270 is actuated to a substantially nonconducting condition, the voltage at the emitter of the transistor Q10 increases to a relatively larger value which is positive with respect to the common conductor N1, as indicated at 880 in FIG. 4C, to reverse bias the diode D35 and to operatively remove the low resistance path between the upper side of the timing capacitor C4 and the common conductor N1 through the diodes D31 and D35. The timing capacitor C4 is then permitted to start accumulating a charge from the output pulses of current from the pulse generating circuit 230 with the voltage across the timing capacitor C4 gradually increasing in accordance with substantially the square of the highest unidirectional voltage across the resistors R1, R2 and R3 and, in turn, with the square of the highest line current flowing through the conductors L1, L2 and L3.

When the transistor 09 is actuated to a substantially saturated condition in response to a predetermined instantaneous overload current flowing in one of the line conductors L1, L2 and L3 as reflected by the highest unidirectional voltage across one of the resistors R1, R2 and R3, as indicated at 820 in FIG. 4A, the capacitor C5 which was previously charged up to a voltage equal to the difference in voltage between the conductors P1 and N1 less the voltage drop across the resistor R17 will rapidly discharge through the emitter-collector path of the transistor 09 until the capacitor C5 is substantially completely discharged. If the highest instantaneous line cur rent flowing in the conductors L1, L2 and L3 and the corresponding highest unidirectional voltage across the resistors R1, R2 and R3 should instantaneously decrease to values below the predetermined or threshold values, as indicated at 821 in FIG. 4A, after the level detecting circuit 260 has operated to actuate the transistor 010 to a substantially nonconducting condition, the transistor 08 will be substantially instantaneously restored to a saturated condition and the transistor ()9 will be substantially instantaneously returned to a substantially nonconducting condition. Since the sum of the voltage drops across the capacitor C5 and the resistor R17 is equal to the voltage difference between the conductors P1 and N1, the voltage across the capacitor C5 following its discharge by the actuating of the transistor O9 to substantially a saturated condition and the instantaneous return of the transistor 09 to a substantially nonconducting condition due to instantaneous changes in the highest line current in said conductors will increase relatively slowly after the transistor ()9 is restored to a substantially nonconducting condition due to the presence of the resistor R17 in the charging path of the capacitor C5. The charging current which flows to the charg ing capacitor C5 after the transistor 09 is returned to a substantially nonconducting condition will produce a gradually decreasing voltage drop across the resistor R17, as indicated at 860 in FIG. 4C, which is sufficient to maintain the transistor Q10 in a substantially nonconducting condition for a predetermined time period or interval after the highest instantaneous unidirectional voltage across the resistors R1, R2 and R3 decreases below the predetermined value or threshold value necessary to actuate the level detecting circuit 260. In other words, if the highest instantaneous line current flowing in the conductors L1, L2 and L3 should exceed a predetermined overcurrent value which corresponds to the highest unidirectional voltage across the resistors R1, R2 and R3, as indicated at 820 in FIG. 4A, and then instantaneously should decrease below the predetermined instantaneous value which corresponds to the highest unidirectional voltage across said resistors, as indicated at 821 in FIG. 4A, the transistor Q10 will be maintained in a substantially nonconducting condition by the timing circuit which includes the capacitor C5 and a resistor R17 which will delay the resetting of the level detecting circuit 260 for a predetermined time period or interval which may, for example, be slightly longer than the time duration of one-half cycle of the alternating current which flows in the conductors L1, L2 and L3.

It the highest of the instantaneous line currents which flow in the conductors L1, L2 and L3 should exceed the predeter mined overload current to which the level detecting circuit 260 responds and then instantaneously decrease for a period of time less than the time delay or interval for which the level detecting circuit 260 is set by the timing circuit which includes the capacitor C5 and a resistor R17, the transistor 010 will be maintained in a substantially noneonducting condition to per mil the timing capacitor C4 to continue accumulating charge from the output pulses of current from the pulse generating circuit 230, as indicated at 860 in FIG. 4C. lf however the time interval between successive periods of instantaneous ovcrcur' rent which correspond to successive periods of instantaneous unidirectional voltage across the resistors RI, R2 and R3, as indicated at 820 in FIG. 4A, should exceed the time delay period for which the level detecting circuit 260 is set by the timing circuit which includes the capacitor C and a resistor R [7, as indicated at 870 in FIG. 4C, the transistor Q then be restored to a substantially saturated condition and rapidly reset the timing capacitor C4 by rapidly discharging the timing capacitor C4 through the circuit which includes the diodes D31 and D35 and the emitter-collector circuitof the transistor 0| 0 to thereby reset the timing capacitor C4 so that the time delay provided by the overall long time delay tripping circuit 200 would have to again start from an initial operating point on the timing capacitor C4. The voltage at the emitter of the transistor Ol0 would then be restored to a negligible value as indicated at the right end of FIG. 4D.

In summary, the level detecting circuit 260 provided a relativcly fast resetting time since the level detecting circuit 260 responds to the instantaneous value of the highest unidirectional voltage across resistors Rl, R2 and R3 and, in turn, to the highest instantaneous line current flowing in the conductors Ll, L2 and L3 to initiate the start of the predetermined time delay providcd by the long time delay tripping circuit 200 but resets the timing capacitor C4 ifthe time interval between successive instantaneous periods of overcurrent above the predetermined or threshold value for which the level detecting circuit 260 is adjusted is longer than the predetermined time period provided by the timing circuit of the level detecting circuit 260 which comprises the capacitor C5 and the resistor R17 which may be, for example, slightly longer than onehalf cycle of the alternating current flowing in the conductors Ll, L2 and L3. It is to be noted that the timing circuit included as part of the level detecting circuit 260 is reset to the beginning of the time delay provided in the resetting of the level detecting circuit 260 each time that the instantaneously highest line current flowing in the conductors Ll, L2 and L3 exceeds the predetermined or threshold value to which the level detecting circuit 260 responds and the timing circuit of the level detecting circuit 260 remains reset at the initial operating point until the highest instantaneous linc current flowing in the conductors L1, L2 and L3 decreases below the predetermined or threshold value. As previously mentioned, the timing circuit ofthe level detecting circuit 260 times out if the time interval between successive instantaneous periods of overcurrent exceeds the predetermined time intcrval for which the timing circuit of the level detecting circuit 260 is set but permits the timing of the long time delay tripping circuit 200 to continue in an uninterrupted fashion if the time interval between successive periods ofinstantaneous overcurrent is less than the predetermined time interval which is provided by the timing circuit of the level detecting circuit 260. In other words, the level detecting circuit 260 provides a rela' tively fast resetting response without chopping or interrupting the effective output of the level detecting circuit 260 as indicated at 880 in FIG. 4D.

It is to be noted that the predetermined overcurrent level to which the level detecting circuit 260 responds is normally relatively lower than the instantaneous overload current to which the instantaneous tripping circuit 300 responds as will be described hereinafter. It is also to be noted that when the transistor 010 which forms the control means 270 is in a substantially saturated condition, the diode D31 is forward biased and the output pulses of current from the pulse generating circuit 230 which flow from the collector ofthc transistor ()6 will flow to the common conductor NI through a current path which extends from the collector of the transistor ()6 through the diodes D30 and D31, the diode D35, and the emitter-collector circuit of the transistor Ol0, Whenever the transistor 010 is actuated to a substantially noneonducting or cutoff condition, the voltage applied at the cathode of the diode D3] from the posilivc conductor P3 through the diode D45, the resistor R35 and the diode D46 will be suflicient to reverse bias the diode D3! and permit the timing capacitor to accumulate a charge from the output pulses of current from the pulse generating circuit 230 which flow from the collector of the transistor 06 through the diode D30 to the upper side of the timing capacitor C4.

in the overall operation of the long time delay tripping circuit 200, when the capacitor C4 is permitted to charge from the output pulses of current of the pulse generating circuit 230, the voltage across the capacitor C4 increases in discrete steps until the voltage at the upper side of the capacitor C4 is sufficiently positive to forward bias the diode D3l. When the diode D31 is forward biased by the voltage at the upper side of the capacitor C4 increasing to a predetermined or threshold value, the output pulses of current from the collector of the transistor 06 are applied through the diodes D30 and D3] to the output circuit 400, as will be explained hereinafter, to actuatc the operation of the output circuit 400 to energize the trip coil 36 of the circuit breaker C8 to thereby actuate the opening of said circuit breaker. Since the average charging current applied to the timing capacitor C4 from the pulse generating circuit 230 when the pulse generating circuit 230 is permitted to charge the capacitor C4 is substantially proportional to the square of the highest unidirectional voltage across the resistors R1, R2 and R3 and, in turn, to the highest line current flowing in the conductors Ll L2 and L3, the time delay required to charge the capacitor C4 to substantially a predetermined or threshold voltage sufficient to actuate the output circuit 400 varies substantially inversely with the square of the highest line current which flows in the conductors LI, L2 and L3. In order to limit the necessary size of the timing capacitor C4 to a practical value which is sufficient to provide the time delay required for different values of overload currents, the magnitude of the output unidirectional current pulses from the transistor O6 is limited to a certain range of current values. Under certain operating conditions, such as relatively lower overload currents, the unidirectional output pulses of current at the collector of the transistor 06 which are applied through the diodes D30 and D31 when the voltage across the capacitor C4 reaches the predetermined or threshold value, may not be sufficient to actuate the operation ofthe output circuit 400.

in order to increase the sensitivity of the long time delay tripping circuit 200 and to ensure that the output pulses of current applied from the long time delay tripping circuit 200 to actuate the output circuit 400 are sufficient for all operating conditions as required in a particular application, the auxiliary pulse generating circuit 240 is connected to the pulse generating circuit 230 to periodically increase the voltage available at the upper side of the timing capacitor C4, More specifically the auxiliary pulse generating circuit 240 is pro vided to periodically increase the voltage between the lower side of the timing capacitor C4 and the common or negative conductor Nl.

More specifically, the auxiliary pulse generating circuit 240 comprises a NPN transistor 03. The base of the transistor 03 is connected to the positive conductor Pl through the resistor R7 and is coupled to the upper base of the unijunction transistor ()4 ol' the pulse generating circuit 230 by the capacitor C2, while the emitter of the transistor O3 is directly con' nected to the common or negative conductor Nl. The collector of the transistor O3 is connected to the positive conductor PI through the collector load resistor R8 and also to the lower side of the timing capacitor C4. It is to be noted that the diode D34 is connected between the lower side of the timing capacitor C4 and the common or negative conductor N] to complete the discharge path for the timing capacitor C4 during the actuation of the output circuit 400 by the long time delay tripping circuit 200, as will be explained hereinafter. The diode D32 which may comprise one or more diodes, as

required in a particular application, is connected between the collector of the transistor ()3 and the common or negative conductor N] to limit the magnitude of the output pulses of voltage from the auxiliary pulse generating circuit 240 to the forward voltage drop of the diode D32.

In the operation of the auxiliary pulse generating circuit 240. the transistor 03 is normally maintained in a substantially saturated condition by the base drive current which flows from the positive conductor Pl through the resistor R7 and the base emitter circuit of the transistor 03 to the negative or common conductor N1. When the transistor ()3 is in a substantially saturated condition, the lower side of the timing capacitor C4 is at substantially the same potential as the common or negative conductor N] since the voltage drop across the collectonemitter circuit of the transistor 03 is substantially negligible when the transistor O3 is in a substantially saturated condition. When however the unijunction transistor 04 of the pulse generating circuit 230 periodically breaks over during the operation of the pulse generating circuit 230. a negative voltage pulse is produced at the upper base of the transistor 04 each time that the transistor 04 breaks over and this negative voltage pulse is transmitted or coupled to the base of the transistor Q3 through the capacitor C2 to thereby actuate the transistor ()3 to substantially a nonconducting or cutoff condition. When the transistor ()3 is periodically actuated to a substantially nonconducting condition by the opera tion of the pulse generating circuit 230, the voltage at the col lector of the transistor 03 increases in a positive direction and raises the voltage at the lower side of the timing capacitor C4 by an amount equal to the forward voltage drop of the diode D32. in the overall operation of the long time delay tripping circuit 200, as the charge on the timing capacitor C4 approaches the predetermined or threshold value necessary to forward bias the diode D31, the auxiliary or supplementary periodic output voltage pulses applied at the lower side of the capacitor C4 effectively increase the voltage at the upper side of the capacitor C4 with respect to the common or negative conductor N] and permit the output pulses of current from the collector transistor 06 to be applied through the diode D3] when the total voltage effective at the upper side of the capacitor C4 reaches the predetermined or threshold value necessary to aciuate the output circuit 400. The operation of the output circuit 400 is thus assured over the entire range of overload currents to which the long time delay tripping circuit 200 responds. It is to be noted that the diode D27 is connected between the base and the emitter of the transistor 03 for the purpose of limiting the change in voltage at the left side of the capacitor C2 when the transistor 03 is periodically actuated to a nonconducting condition to thereby assist in controlling the width of the output pulses at the collector of the transistor 03 and protecting the base-emitter circuit of the transistor 03 from excessive reverse bias voltages.

Output Circuit 400 In general, the output circuit 400 of the protective device shown in FIG. 1 is connected to the long time delay tripping circuit 200 to respond to substantially a predetermined charge on the capacitor C4 which corresponds to a predetermined or threshold voltage across said capacitor to actuate the energization of the trip coil 36 of the circuit breaker CB following a predetermined time delay after the operation of the level delecting circuit 260 permits the timing capacitor C4 to start ac- :umulating the charge. More specifically the output circuit I comprises an output level detecting circuit 410 which is :onnected to the timing capacitor C4 through the diode D3]. he semiconductor switching device Ol7 whose operation is ictuated by the output level detecting circuit 4H) and the auxliary potential source 420 which is provided to maintain cerain operating potentials during certain operating conditions. is will be explained hereinafter.

The output level detecting circuit 4l0 is of the breakover ype in that once the operation of the output level detecting circuit 410 is initiated, the operation of said circuit continues or proceeds by regenerative action until the operation of said circuit is completed. The output level detecting circuit 410 comprises the PNP transistor 015 and the NPN transistor Ql6. The emitter of the transistor Ol5 is connected to the upper side of the timing capacitor C4 through the diode D3], while the base of the transistor 015 is connected to the P3 through the resistor R35 and the forward connected diode D45. The collector of the transistor 015 is connected to the base ofthe transistor Q16 through the diode D47 and also to the control means of the power supply input circuit I00 through the isolating diode D48 in order to prevent the opera tion of the output circuit 400 in the event that the energy storing capacitor Cl3 of the power supply input circuit [00 is not fully charged. as previously explained. As shown in FIG. 2. the collector of the transistor Ql6 is directly connected to the base of the transistor 015, while the emitter of the transistor 016 is connected to the common or negative conductor NI through the resistor R34 and also to the gate electrode of the silicon controlled rectifier or semiconductor switching device Q17. The resistor R33 is connected between the emitter and the base of the transistor Q15 in order to normally maintain the potential at the emitter of the transistor OlS at substan tially the same potential as at the base of the transistor 015. In order to protect the emitter-base circuit of the transistor 015 from excess reverse bias during certain operating conditions the diode D46 is connected between the emitter and the base of the transistor OlS to limit the reverse voltage across the emitter-base circuit of the transistor 015 to the forward volt age drop of the diode D46. The capacitor Cll is connected between the emitter and the base of the transistor 015 to provide some degree of noise suppression in the operation of the output level detecting circuit 410 by bypassing transient volt age surges which may occur in the overall operation of the protective device shown in FIG. 1 around the emitter-base circuit of the transistor 015. The resistor R32 is connected between the base of the transistor Q16 and the common or negative conductor Nl to provide a shunt path around the base-emitter circuit of the transistor 016 for the leakage current which might flow at relatively high environmental temperatures from the collector to the base of the transistor 016. The resistor R32 prevents this leakage current from flowing from the base of the emitter of the transistor Q16 and being amplified by the current gain of the transistor 016 which might cause improper tripping operations due to the gating of the silicon controlled rectifier Q17. The resistor R32 also determines the amount of current at the emitter of the transistor 015 which is necessary to actuate the operation of the output level detecting circuit 410.

The auxiliary potential source 420 is connected to the output level detecting circuit 410 to temporarily maintain the voltage at the base of the transistor Q15 whenever the overall protective device shown in FIG. 1 is deenergized. The auxiliary potential source 420 maintains this voltage sufficiently long enough to prevent an improper operation of the output level detecting circuit 400 when the voltages at the positive conductors Pl, P2 and P3 collapse at a relatively fast rate and the voltage on the timing capacitor C4 might be sufficient to actuate the operation of the output level detecting circuit 410 and to cause an improper tripping operation of the circuit breaker C8 The auxiliary potential source 420 comprises the diode D45 which is connected between the positive conductor P3 and the right end of the resistor R35, the capacitor C12 which is connected between the junction point of the resistor R35 and the diode D45 and the common or negative conductor N1, and the resistor R36 which is connected between the upper side of the capacitor Cl2 and the common or negative conductor N I. It is to be noted that the resistor R36 provides a relatively slow discharge path for the capacitor C12 after the overall protective device shown in HO. 1 has been deenergized for a certain time period and the auxiliary potential source 420 has performed its intended purpose. It is to be noted that the auxiliary potential source 420 also prevents improper tripping operations in the event that the overall protective device should be temporarily deenergized due to a temporary loss of power.

in order to energize the trip coil 36 of the circuit breaker CB in response to the operation of the output level detecting circuit 410, the anode of the silicon controlled rectifier or semiconductor switching device 017 is connected to the positive conductor P1 through the resistor R37, while the cathode of the silicon controlled rectifier O 17 is connected to the common or negative conductor N1. The trip coil 36 is electrically connected in parallel with the resistor R37 between the positive conductor P1 which, in turn, is connected to one side of the supply capacitor C13 and the junction point between the resistor R37 and the anode of the silicon controlled rectifier 017. More specifically, the trip coil 36 is connected between the terminal 414, as shown in FIG. 1, which, in turn, is connected to the positive conductor P1 and the terminal 422 which is connected, in turn, to the junction point between the resistor R37 and the anode of the silicon controlled rectifier 017. In order to prevent an improper operation of the silicon controlled rectifier 017 due to transient voltage surges which may occur during the overall operation of the protective device shown in FIG. 1, a noise suppression network, which includes the resistor R44 and the capacitor C17 connected in series, is connected between the anode and the cathode of the silicon controlled rectifier 017 to bypass transient voltage surges around the silicon controlled rectifier 017.

In the overall operation of the output circuit 400, when the level detecting circuit 260 of the long time delay tripping circuit 200 permits the timing capacitor C4 to accumulate charge from the pulse generating circuit 230, the voltage across the timing capacitor C4 increases in discrete steps at a rate which varies substantially with the square of the highest line current which flows in the conductors L1, L2 and L3, as previously explained, until the voltage across the timing capacitor C4 is sufficient to forward bias the diode D31. When the diode D3] is forward biased by the voltage at the upper side of the timing capacitor C4 which is periodically increased by the auxiliary pulse generating circuit 240, as previously explained, an input current for the output circuit 400 flows from the collector of the transistor 06 through the diodes D30 and D31, through the emitter-base circuit of the transistor 015 of the output level detecting circuit 410 to thereby increase the current which flows from the emitter to the collector of the transistor Q15. The increased current flow through the emitter-collector circuit of the transistor Q flows through the diode D47 and the baseemitler circuit of the transistor 016. When the transistor Q16 starts to conduct current in its base-emitter circuit, the current which flows from the collec tor to the emitter of the transistor 016 also increases to thereby additionally increase the current flow from the emitter to the base of the transistor 015. It is to be noted that the current which flows in the collector-emitter path of the transistor 016 also flows from the positive conductor P3 through the diode D45 and the resistor R35 through the collector-emitter circuit of the transistor Q16 and to the common conductor N1 through the resistor R34. The efl'ect of the increase in the collector-emitter current of the transistor Q16 and its consequent effect on the emitter-base current of the transistor O15 increases until both of the transistors Q15 and 016 are actuated to a substantially saturated condition. The output current of the output level detecting circuit 410 from the emitter of the transistor 016 also flows through the gate of the silicon controlled rectifier Q17 into the anode of the silicon controlled rectifier 017 to thereby actuate the silicon controlled rectifier 017 to a substantially conducting condi tion. When the silicon controlled rectifier 017 is actuated to a substantially conducting condition, the trip coil 36 is energized by the current which flows from the positive conductor P1 through the trip coil 36 and through the anode-cathode circuit of the silicon controlled rectifier Q17 to the common or negative conductor N1 to thereby actuate a tripping operation of the circuit breaker CB. It should be noted that the current which energizes the trip coil 36 flows from the right side of the energy storing capacitor C13 through the positive conductor P1, the trip coil 36, the anode-cathode circuit of the silicon controlled rectifier 017 to the common conductor N1 and then to the left side of the capacitor C13.

in the event that the capacitor C13 is not charged sufficiently to energize the trip coil 36, the control means will prevent the operation of the output circuit 400 by providing a relatively low resistance path from the collector to the transistor 015 through the diode D48 which will then be forward biased and through the collector-emitter circuit of the transistor 02 of the control means 150 to the common or negative conductor N1 which prevents the regenerative operation of the output circuit 400.

It is to be noted that after the trip coil 36 is energized by the discharge of the capacitor C13 through said trip coil and the silicon controlled rectifier 017, the resistor R37 which is con nected in series with the anode cathode circuit of the silicon controlled rectifier Q17 provides a circulating path to dissipatc the stored energy in the trip coil 36 which normally involves an inductive device and thereby limits the inverse voltage applied to the silicon controlled rectifier 017 to a value within the rating of the silicon controlled rectifier 017.

As previously mentioned, the auxiliary pulse generating circuit 240 is provided to periodically increase the voltage at the lower side of the timing capacitor C4 and in effect at the upper side of the timing capacitor C4 in order to insure that the input current applied to the output circuit 400 will be sufficient over the entire range of overload currents to which the long time delay tripping circuit 200 is intended to respond.

in summary, the overall operation of the protective device shown in H6. I due to the long time delay tripping circuit 200 is such that the tripping time in seconds of the associated circuit breaker varies substantially inversely with the square of the overcurrcnt over a predetermined range or overcurrents to which the long time delay tripping circuit 200 responds. The predetermined highest line current which actuates the start of the time delay provided in the operation of the long time delay tripping circuit 200 may be controlled between predetermined limits by the setting of the rheostat R39 which forms part of the level detecting circuit 260 of the long time delay tripping circuit 200. The minimum time delay characteristic provided by the time delay tripping circuit 200 may be obtained by the adjustment of the rheostat R38 which forms part of the second current circuit means 220 of the maximum time delay characteristic provided by said long time delay tripping circuit may be similarly obtained by the adjustment of the rheostat R38 with a family of intermediate time delay characteristics being available by the adjustment of the rheostat R38 between the limiting adjustments. in other words, the long time delay tripping circuit 200 provides substantially an I, =K (where K equals a constant and t equals tripping time) operating characteristic which may be varied in a substantially continuous manner between a minimum time delay characteristic and a maximum time delay characteristic by the adjustment of the rheostat R38 which, in effect, varies the con stant to which F, is substantially equal over a predetermined operating range of overload currents. As previously explained, if the highest line current flowing in the conductors L1, L2 and L3 exceeds the predetermined or threshold value to which the level detecting circuit 260 responds as determined by the setting of the rheostat R39, the timing capacitor C4 will be permitted to start accumulating a charge from the pulse generating circuit 230. If however the highest line current flowing in the conductors L1, L2 and L3 then instantaneously decreases to a value less than the predetermined value to which the level detecting circuit responds and remains less than the predetermined value, the timing capacitor C4 will be reset by the level detecting circuit 260 after a predetermined time interval or delay which depends upon the operation of the timing circuit which forms part of the level detecting 260 and which may be adjusted or selected to be slightly longer than one-half cycle of the alternating current flowing in the conductors L1, L2 and L3 assuming that the last-mentioned time interval before the resetting of the capacitor C4 ends before the voltage across the capacitor C4 is sufficient to actuate the operation of the output level detecting circuit 410. The reset of the timing capacitor C4 will be accomplished by restoring the control means 270 which comprises the transistor 010 to substantially a saturated position which rapidly discharges the timing capacitor C4 at the end of the time interval just mentioned. it is to be noted that the control means 270 is of the emitter follower type.

instantaneous Tripping Circuit 300 Referring now to the instantaneous tripping circuit 300 in dicated in block form in Fig. l and shown in detail in FIG. 2, the instantaneous tripping circuit 300, in general, is connected between the first auctioneering circuit H of the power supply input circuit I00 and the level detecting circuit 410 of the output circuit 400 to actuate the energization of the trip coil 36 of the circuit breaker CB when the highest instantaneous line current flowing in the conductors Ll, L2 and L3 increases above or exceeds substantially a predetermined or threshold value without any intentional time delay.

More specifically, the instantaneous tripping circuit 300 as shown in FIG, 2 comprises a PNP transistor Oil! and a voltage dividing network which includes the rheostat R42, the resistor R24 and the resistor R89 which are connected electrically in series with one another between the variable voltage output conductor VI of the first auctioneering circuit 110 and the positive conductor P3. The emitter of the transistor 018 is connected to the junction point between the resistors R24 and R89, while the base of the transistor 018 is connected to the positive conductor P2 in order that the forward voltage drop across the diode D23 which may include one or more forward connected diodes in a particular application compensate the input voltage of the instantaneous tripping circuit 300 for the forward voltage drop across one of the diodes D17, D18 or Dl9 of the first auctionecring circuit 110 and for the forward voltage drop across the emitter-base circuit of the transistor 018 during the operation of the instantaneous tripping circuit 300. The diode D39 is connected between the emitter and the base of the transistor Q18 in order to protect the emitter-base circuit of the transistor 018 from excessive reverse bias by limiting the maximum reverse voltage applied to the emitterbase circuit of the transistor 018 to the forward voltage drop of the diode D39. The collector of the transistor 018 is connected to the common conductor N] by the collector load re sistor R25. The output of the instantaneous tripping circuit 300 at the collector of the transistor Ql8 is connected to the emitter of the transistor Q of the output level detecting circuit 410 by the isolating diode D40 whose anode is connected to the collector of the transistor Q18 and whose cathode is connected to the emitter of the transistor Q15. The capacitor C8 is connected electrically in parallel with the resistor R25 between the collector of the transistor Q18 and the common conductor N1 in order to provide a predetermined degree of noise suppression in the operation of the instantaneous tripping circuit 300 by diverting the output of the instantaneour. tripping circuit 300 to the common conductor Nl when the output is due to transient voltage surges which may occur during the operation of the overall protective device shown in FIG. 1 and also to provide a pulse of discharge current to the output level detecting circuit 410 of the output circuit 400 during the operation of the instantaneous tripping circuit 300 to insure that the transistors CR5 and 016 are both actuated to substantially saturated conditions and to insure that the silicon controlled rectifier Q17 is actuated to a substantially conducting condition to energize the trip coil 36 during the overall operation of the protective device shown in FIG. I.

In the operation of the instantaneous tripping circuit 300. the base of the transistor 018 is held at the regulated, unidirectional potential at the positive conductor P2. The voltage at the emitter of the transistor Q18 varies with and is directly proportional to the highest unidirectional voltage across the resistors R], R2 and R3 and, in turn, to the highest instantaneous line current flowing in the conductors Ll, L2 and L3. More specifically, the voltage at the emitter of the transistor 018 is equal to the voltage at the positive conductor P3 plus the voltage drop across the resistor R89 which depends, in part, on the setting of the rheostat R42. As long as the highest instantaneous linc current flowing in the conductors Ll, L2 and L3 remain below substantially a predetermined or threshold value, the emitter-base circuit of the transistor 018 is reverse biased and the transistor 018 is substantially nonconducting or cutoff. As long as the transistor Q18 is substantially nonconducting or cutoff, the current flow through the resistor R25 in the collector circuit of the transistor Q18 is substantially negligible and the potential of the anode of the diode D40 is relatively close to the potential at the common or negative conductor N! with the diode D40 being normally reverse biased or blocked due to the potential which is applied to the cathode of the diode D40 from the positive conductor P3 through the diode D45, the resistor R35 and the diode D46. When the highest instantaneous line current flowing in one of the conductors Ll, L2 and L3 exceeds substantially a predetermined or threshold value to which the instantaneous tripping circuit 300 is adjusted to respond by the setting of the rheostat R42, and the corresponding highest instantaneous unidirectional voltage across the resistors Rl, R2 and R3 exceeds substantially a predetermined value, the voltage at the emitter of the transistor Q18 increases in a positive direction sufficiently to forward bias the emitter-base circuit of the transistor Q18 and to actuate the transistor 018 to substantially a saturated condition. Due to the increased current flow in the emitter-collector path of the transistor 018, the voltage drop across the resistor R25 increases to thereby forward bias the diode D40 and the output current of the instantaneous tripping circuit 300 from the collector of the transistor Q18 flows through the diode D40 and into the emitter-base circuit of the transistor 015 to actuate the output level detecting circuit 410 to, in turn, actuate the silicon c0ntrolled rectifier Ql7 to a substantially conducting condition and to energize the trip coil 36, as previously explained in c0nnection with the operation of the long time delay tripping circuit 200. As previously mentioned, when the highest instantaneous line current flowing in the conductors L1, L2 and L3 exceeds substantially a predetermined or threshold value for which the rheostat R42 is adjusted, the instantaneous tripping circuit actuates the energization of the trip coil 36 in a sub stantially instantaneous manner without giving any intentional time delay. In the operation of the instantaneous tripping circuit 300 it is to be noted that as the highest instantaneous line current in the conductors L1, L2 and L3 increases toward the predetermined value to which the instantaneous tripping circuit 300 responds, the control means 270, which form part of the level detecting means or circuit 260 of the long time delay tripping circuit 200 will be actuated from a normally saturated condition to a substantially nonconducting or cutoff condition prior to the operation of the instantaneous tripping circuit 300 to thereby eliminate the relatively low resistance path to the common conductor N! from the emitter of the transistor 015 which would otherwise divert the output current of the instantaneous tripping circuit 300 away from the emitter of the transistor Q15.

it is to be noted that the setting of the instantaneous tripping circuit 300 determines the upper limit or end of the range of overload currents to which the long time delay tripping circuit 200 responds, since when the highest instantaneous line cur rent flowing in the conductors L1, L2 and L3 exceeds the predetermined or threshold value to which the instantaneous tripping circuit 300 responds, the trip coil 36 of the circuit breaker CB will be energized substantially instantaneously as determined by the operative characteristics of the instantaneous tripping circuit 300 without any intentional time delay being introduced prior to the energization ofthe trip coil 36. it is also important to note that the energization of the trip coil 36 in response to the long time delay tripping circuit and the instantaneous tripping circuit 300 occurs independently either after a predetermined time delay which varies substantially invcrsely with the square of the overcurrent in the case of the long time delay tripping circuit 200 or substantially instantaneously in response to the operg tionpf the instantaneous tripping circuit 300. The operatrbn of the instantaneous tripping circuit 300 may be inhibited or prevented in response to the closing of the main contacts BC], BC2 and 8C3 by the use of an auxiliary contact whose operation is coordinated with those of the main contacts of the circuit breaker CB and which is connected to the terminal 144 of the power supply input circuit 100 of the protective device shown in FIG. I and which, as shown in FIG. 2, is connected to the collector of the transistor 018 of the instantaneous tripping circuit 300 as disclosed and claimed in copending application Ser. No. 765,552 filed by W, H. South and J. H. Taylor which is assigned to the same assignee as the present application.

Short Delay Tripping Circuit S Referring now to the short delay tripping circuit 500 which is indicated in block form in FIG. 1 and shown in detail in FIG. 3, the short delay tripping circuit 500 is connected between the first auctioneering circuit 110 and the output circuit 400 to respond to the highest instantaneous line current flowing in the conductors L] L2 and L3 when the highest instantaneous line current succeeds substantially a predetermined or threshold value to actuate the output circuit 400 to energize the trip coil 36 following a substantially fixed or predetermined time delay which remains at the same predetermined value independently of the magnitude of the highest instantaneous current in excess of the predetermined value to which the short delay tripping circuit 500 responds. It is to be noted that the short delay tripping circuit 500 may be employed where required in combination with the long time delay tripping circuit 200 and the instantaneous tripping circuit 300 and that the short delay tripping circuit 500 independently actuates the output circuit 400 to energize the trip coil 36 with the predetermined current to which the short delay tripping circuit 500 responds being coordinated with the range ol'over' load current to which the long time delay tripping circuit 200 responds and the predetermined instantaneous current to which the instantaneous tripping circuit 300 responds.

More specifically, the short delay tripping circuit 500 comprises a level detecting circuit 510 which includes the PNP transistors Q11 and Q12 and a voltage dividing network which controls the conducting state of a control means which comprises the diode D38 and which has a time delay reset operation of the same general type, as previously described in detail in connection with the level detecting circuit 260 of the long time delay tripping circuit 200. The voltage dividing network of the short delay tripping circuit 500 includes the resistors R19 and R20 along with the rheostat R40 which are connected in series with one another between the variable voltage output conductor V1 of the first auctioneering circuit 110 and the positive conductor P3. The base of the transistor 011 is connected to the junction point between the resistors R19 and R20, while the emitter of the transistor 011 is connected to the positive conductor PI. The diode D36 is connected between the base and the emitter of the transistor O1] to protect the emitter-base circuit of the transistor Q11 from execssive reverse bias by limiting the maximum reverse voltage applied to the emitter-base circuit of the transistor 011 to the forward voltage drop of the diode D36. The input voltage of the short delay tripping circuit 500 which is the sum of the voltage drops across the rheostat R40 and the resistor R19 is substantially equal to the highest unidirectional voltage across the resistors R1, R2 and R3 and, in turn, is directly proportional to the highest instantaneous line current flowing in the conductors L1, L2 and L3. The forward voltage drop in the emitter-base circuit of the transistor Q11 compensates the input voltage of the short delay tripping circuit 500 for the forward voltage drop across one of the diodes D17, D18 and D19 of the first auctioneering circuit 110. The collector of the transistor 011 is directly connected to the base of the transistor Q12 and also to the common conductor Nl through the collector load resistor R21. The emitter of the transistor QllZ is directly connected to the positive conductor Pl, while the collector of transistor Ol2 is connected to the common conductor N1 through the collector load resistor R22 and through the diode D38 to the upper side of the timing capacitor C7 of the short delay tripping circuit 500. in order to delay the reset of the short delay gripping circuit 500 following the end ofa period oftime during which the highest instantaneous line current flowing in the conductors L1, L2 and L3 exceeds the predetermined or threshold value to which the short delay tripping circuit is adjusted to respond by the setting of the rheostat R40, the capacitor C6 is connected between the emitter and the collector of the transistor Q12 between the positive conductor P1 and the upper end of the resistor R22. In order to provide a substantially fixed or predetermined time delay between the start of an instantaneous overcurrent which exceeds the predetermined value and to which the short delay tripping circuit 500 is adjusted to respond, an RC timing circuit is provided as part of the short delay tripping circuit 500 which includes the rheostat R4], the resistor R23 and the timing capacitor C7, with the rheostat R41 and the resistor R23 being connected in series with one another between the posi tive conductor P1 and the upper side of the timing capacitor C7. The upper side of the timing capacitor C7 is also connected to the emitter of the transistor 015 which forms part of the output level detecting circuit 410 of the output circuit 400 through the normally reverse biased or blocked diode D37. The lower side of the timing capacitor C7 of the short delay tripping circuit 500 is connected by the conductor 286 to the output of the auxiliary pulse generating circuit 240 at the cob lector of the transistor 03 which forms part of the auxiliary pulse generating circuit 240 in order that the lower side of the capacitor C7 be periodically raised in voltage with respect to the common conductor Nl to thereby periodically increase the effective voltage at the upper side of the capacitor C7v In the operation of the short delay tripping circuit 500, it is important to note that the output of the first auctioneering cir cuit at the variable voltage conductor V! which forms the input for the short delay tripping circuit 500 is unfiltered and therefore the input voltage of the short delay tripping Circuit 500 which appears across the rheostat R40 and the resistor R19 comprises a series of unidirectional voltage pulses each having substantially the same configuration as one-half cycle of the alternating current which flows in the conductors L1, L2 and L3 similarly to the waveforms shown in FIG. 4A and described in detail in connection with the level detecting circuit 260 of the long time delay tripping circuit 200. In other words, the input of the short delay tripping circuit 500 at the variable voltage conductor Vl varies substantially instantaneously with the highest line current flowing in the conductors Ll, L2 and L3.

As long as the highest instantaneous line current flowing in the conductors L1, L2 and L3 remains below substantially a predetermined or threshold value and the corresponding highest instantaneous unidirectional voltage across the resistors R1, R2 and R3 remains below a corresponding predetermined or threshold value, the transistor Q11 will be in a normally saturated condition since the emitter-base circuit of the transistor 011 will be forward biased with the voltage at the conductor P1 with respect to the common conductor being greater than the voltage at the base of the transistor Q11 with respect to the common conductor N1. The predetermined highest instantaneous current to which the short delay tripping circuit 500 is adjusted to respond is determined by the setting of the rheostat R40. As long as the transistor 011 is in a normally saturated condition, the emitter-base circuit of the transistor Q12 will be biased at substantially zero voltage and the transistor 012 will be maintained in a substantially nonconducting or cutoff condition. When the transistor Q12 is in a substantially cutoff condition, the voltage drop across the re sistor R22 due to the emitter-collector current of the transistor CD will be substantially negligible and the voltage at the cathode of the diode D38 which forms the control means of the short delay tripping circuit 500 will be relatively close to the voltage at the common conductor N1 with the diode D38 being forward biased to prevent the timing capacitor C7 from accumulating a charge from the positive conductor Pl through the rheostat R41 and the resistor R23, Since the cathode ofthe diode D37 is normally maintained at a positive voltage with respect to the common conductor Nl through the diode D45, the resistor R35, the diode D46 and the voltage at the positive conductor P3, the diode D37 and normally be reverse biased or blocked since the voltage at the anode ofthc diode D37 will be equal to the sum of the forward voltage drop of the diode D38 and the substantially negligible voltage drop across the resistor R22 as long as the highest in stantancous line current flowing in the conductors L1, L2 and and L3 remains below the predetermined or threshold value to which the short delay tripping circuit is adjusted to respond by the setting of the rheostat R40. it is to be noted that as long as the transistor 012 is in a normally substantially nonconducting or cutoff condition, the capacitor C6 which is connected between the emitter and the collector of the transistor Q12 will be charged up to a voltage which is equal to the difference in voltage between the conductors P1 and N1 less a relatively low voltage drop across the resistor R22.

When the highest instantaneous current flowing in the com ductors Ll, L2 and L3 exceeds substantially a predetermined or threshold value to which the short delay tripping circuit 500 is adjusted to respond by the setting of the rheostat R40, the current which flows in the voltage dividing network which in cludes the rheostat R40, the resistor R19, and the resistor R20 will increase substantially instantaneously until the voltage at the base of the transistor Oll increases in a positive direction to reverse bias the emitter-base circuit of the transistor Qll which will then be actuated to a substantially nonconducting condition, When the transistor 01! is actuated to substantially a nonconducting or cutoff condition, the current in the emitter-collector path of the transistor Qll will decrease to a negligible value and the current which flows in the resistor R2] will now flow from the positive conductor Pl through the emitter-base circuit of the transistor Ql2. The transistor 012 will then be actuated to substantially a saturated condition. When the transistor OH is actuated to a substantially saturated condition, the current in the emitter-collector path of transistor 012 will increase to thereby cause an increased voltage drop across the resistor R22 which will then reverse bias or block the diode D38 and permit the timing capacitor C7 to start charging from the positive conductor Pl through the rheostat R41 and the resistor R23. Assuming that the over' current condition to which the short delay tripping circuit is adjusted to respond continues for substantially a predeter' mined or fixed time delay as determined by the setting of the rheostat R4l, the resistor R23 and the capacitor C! which form a timing circuit which is charged from the regulated voltage between the conductors P1 and N1, the voltage at the upper side of the timing capacitor C7 which is periodically increased by the auxiliary voltage pulses from the auxiliary pulse generating circuit 240 which forms part of the long time delay tripping circuit 200 will be sufficient to forward bias the diode D37. When the diode D37 is forward biased, current will flow from the conductor Pl through the rheostat R41 and the resistor R23 to cause a base drive current to flow through the diode D37 into the emitter-base circuit of the transistor Q of the output level detecting circuit 410 to actuate the silicon controlled rectifier Q17 to a substantially conducting condition to thereby energize the trip coil 36 of the circuit breaker CB and to actuate the circuit breaker CB to an open condition, as previously explained in detail in connection with the long time delay tripping circuit.

It is to be noted that when the transistor 012 is actuated to a substantially saturated condition in response to the highest instantaneous current which flows in the line conductors Ll, L2 and L3, the capacitor C6 which forms a timing circuit with the resistor R22 will rapidly discharge through the cmitter collector path of the transistor Ol2, If the highest instantaneous cur rent flowing in the conductors Ll, L2 and L3 exceeds the predetermined value to which the short delay tripping circuit 500 is adjusted to respond by the setting of the rheostat R40 and then instantaneously decreases below the predetermined value, the transistor Qll will substantially instantaneously be returned to a saturated condition and the transistor Ol2 will be substantially instantaneously restored to a substantially nonconducting condition. When the transistor 012 is restored to a nonconducting condition, the capacitor C6 will then start to charge from the conductors PI and N1 through the resistor R22, While the capacitors C6 is charging, the voltage across the resistor R22 will gradually decrease similarly to the voltage across the resistor R17 previously described in connection with the level detecting circuit 260 until the diode D38 is again forward biased to thereby rapidly discharge the timing capacitor C7, if the overall time delay provided by the short delay tripping conduit 500 has not been completed. in other words, after the operation of the short delay tripping circuit 500 is actuated by the highest instantaneous current flowing in the conductors L1, L2 and L3 and then the highest instantancous current flowing in said conductors decreases below the predetermined value necessary to actuate the short delay tripping circuit 500 for a predetermined time period which is determined by the values of the capacitor C6 and the resistor R22 and the voltage between the conductors P1 and N1, the resetting of the short delay tripping circuit will be delayed for a predetermined time interval which may be slightly longer than one-half cycle of the alternating current flowing in the conductors Ll, L2 and L3 similarly to the operation of the level detecting circuit 260 of the long time delay tripping circuit 200, as previously described in detail. On the other hand, if the highest instantaneous current flowing in the conductors Ll, L2 and L3 exceeds substantially a predetermined or threshold value to which the short delay tripping circuit 500 is adjusted to respond by the setting of the rheostat R40 and then decreases for a period of time less than the time delay provided in the reset short delay tripping circuit 500, the tiniing out or accumulation of charge on the timing capacitor C7 will continue in an uninterrupted fashion. It is to be noted that the substantially predetermined or fixed time delay provided in the overall operation of the short delay tripping circuit 500 which is determined by the timing circuit which includes the resistor R23, the rheostat and the timing capacitor C7 is substantially independent of the magnitude of the highest instantaneous line current in the conductors L1, L2 and L3 for values of instantaneous line current in excess of the predetermined value to which the short delay tripping circuit 500 is adjusted to respond by the setting of the rheostat R40 and that the time delay provided in the operation of the short delay tripping circuit 500 may be adjusted or varied by the setting of the rheostat R414 Where provided, the short delay tripping circuit 500 determined by the predetermined instantaneous overcurrent to which it is adjusted to respond by the setting of the rheostat R40, the upper limit of the range of overcurrents to which the long time delay tripping circuit 200 will respond in a particular application since if the highest instantaneous line current flowing in the conductors Ll, L2 and L3 exceeds the predetermined value to which the short delay tripping circuit is adjusted to respond by the setting of the rheostat R40, the output circuit 400 will be actuated to energize the trip coil 36 after substantially a predetermined or fixed time delay independent of the value of the highest instantaneous overcurrent in excess of the instantaneous overcurrent to which the short delay tripping circuit 500 is adjusted to respond which is normally shorter in duration than the minimum time delay provided in the operation of the long time delay tripping circuit 200. It is to be noted that the reset of the short delay tripping circuit 500 is accomplished by the discharge of the capacitor C7 through the diode D38 and the resistor R22 to the common conductor Nl rather than employing a control means of the emitter follower type such as the control means 270 which forms part ofthe level detecting circuit 260 of the long time delay tripping circuit 200 since the timing capacitor C7 is normally of a lower value than the timing capacitor C4 which forms part of the long time delay trippiiig circuit 200. In summary, it is important to note that the short delay tripping circuit 500 where provided is arranged to independently actuate the output circuit 400 along with the long time delay tripping circuit 200 and the instantaneous tripping circuit 300 where provided.

Ground Current Tripping Circuit 600 Referring now to the ground current tripping circuit 600 which is indicated in block form in FIG. I and which is shown in detail in FIG. 3, the ground current tripping circuit 600, in general, is connected between the ground current transformer T4 and the output circuit 400 to actuate the output circuit 400 to energize the trip coil 36 of the circuit breaker CB when the magnitude of the ground current as sensed by the transformer T4 exceeds substantially a predetermined or threshold value. More specifically, the primary winding of the ground current transformer T4 is connected between the neutral conductor NT] of the current transformers CTl, CT2 and CT3 and the neutral conductor NT2 of the interposing transformers Tl, T2 and T3. The terminal 42 at the upper end of the primary winding of the transformer T4 may be connected to the ground conductor (not shown) of the electrical system which includes the conductors L1, L2 and L3 and which is provided with ground current protection where desired in a particular application. The output ground current of the transformer T4 which is available at the conductors Gl2 and G13 is applied at the input terminals 612 and 6l4, respectively, of a full wave bridge type rectifier circuit which includes the diodes Dl D2, D3 and D4 to obtain a unidirectional current output which is directly proportional to and varies in a substantially linear manner with the ground current in the electrical system being protected. The positive output terminal of the full-wave bridge-type rectifier which includes the diodes Dl through D4 is connected to the positive conductor PI through the resistor R28 to develop a unidirectional voltage across the resistor R28 which is directly proportional to and varies in a substantially linear manner with the ground current in the electrical system being protected. The negative output terminal of the full-wave bridge-type rectifier which includes the diodes D1 through D4 is connected to the common or negative conductor N I.

More specifically, the ground current tripping circuit 600 includes a level detecting circuit 610 and a time delay circuit 620 which provides a substantially predetermined or fixed time delay between the time die ground current exceeds substantially a predetermined or threshold value and the time that the trip coil 36 is energized through the output circuit 400. The level detecting circuit 6l0 of the ground current tripping circuit 600 includes a time delay reset operation similar to that of the level detecting circuit 260 of the long time delay tripping circuit 200 and the level detecting circuit 510 of the short delay tripping circuit 500, as just described. In particular, the input of the level detecting circuit 610 comprises the voltage dividing network which includes the resistors R26 and R27 which are connected in series with one another between the positive output terminal of the full-wave bridge-type rectifier which includes the diodes Dl through D4 and the positive conductor P3. The level detecting circuit 610 also includes the PNP transistors Q13 and 014. The base of the transistor 013 is connected to the junction point between the resistors R26 and R27, while the emitter of the transistor Q13 is connected to the positive conductor Pl. In order to protect the emitterbase circuit of the transistor Q13 from excessive reverse bias by limiting the reverse emitter-base voltage, the diode D41 is connected between the base and the emitter of the transistor 013 to limit the voltage between the emitter and the base of the transistor 013 to the forward voltage drop of the diode D41 The collector of the transistor 013 is connected to the common conductor Nl through the collector load resistor R29 and also to the base of the transistor Ql4. The emitter of the transistor Ol4 is connected to the positive conductor Pl, while the collector of the transistor 014 is connected to the common conductor Nl through the collector load resistor R30. The collector of the transistor Q14 is also connected to the upper side of the timing capacitor C10 through the normally forward biased diode D44. in order to delay the reset of the ground current tripping circuit after the ground current exceeds substantially a predetermined or threshold value and then decreases below the predetermined or threshold value before the time delay provided in the operation of the ground current tripping circuit 600 by the timing circuit 620 is completed, the capacitor C9 is connected between the emitter and the collector of the transistor OH.

The time delay circuit 620 of the ground current tripping circuit 600 comprises the rheostat R43 and the resistor R3] which are connected in series with one another between the positive conductor Pl and the upper side of the timing capacitor C10, which is connected in series with the rheostat R43 and a resistor R3] between the positive conductor P1 and the common conductor Nl, The upper side of the timing capacitor C10 is also connected to the emitter of the transistor 015 which forms part of the output level detecting circuit 410 through the normally reverse biased or blocked isolating diodc D43. It is to be noted that the ground current tripping circuit 600 is of the type which is disclosed and claimed in copending application Ser. No. 765,583, filed concurrently by J. D. Watson and which is assigned to the same assignee as the present application.

In order to prevent the control means 270 which comprises the transistor QlO and which forms part of the level detecting circuit 260 of the long time delay tripping circuit 200 from forming a low resistance path between the cathode of the diode D43 and the common conductor N1 during the operation of the ground current tripping circuit 600 which would otherwise prevent the ground current tripping circuit 600 from actuating the operation of the output circuit 400, the diode D42 is connected between the collector of the transistor Q14 and the base of the transistor 010, as will be explained hereinafter.

In the operation of the ground current tripping circuit 600, as long as the ground current in the electrical system being protected remains below substantially a predetermined or threshold value as sensed by the transformer T4, the emitterbase circuit of the transistor 013 will be forward biased since the voltage at the emitter of the transistor 0]."! which is the same as the regulated voltage at the positive conductor Pl will be greater than the voltage at the base of the transistor 013 which is equal to the voltage at the positive conductor P3 plus a voltage drop across the resistor R27. As long as the transistor Ql3 is in a substantially saturated condition due to the forward biasing ofits emitter-base circuit, the emitter-collector current of the transistor Q13 will produce a voltage drop across the resistor R29 which results in a substantially zero voltage bias of the base-emitter junction of the transistor Q14 and the transistor Q14 which will be maintained in a normally substantially cutoffor nonconducting condition. As long as the transistor 014 is substantially nonconducting or cutoff, the voltage drop across the resistor R30 will be substantially negligible or at a relatively low value and the diode D44 will be forward biased due to the voltage at the positive conductor Pl which is applied to the anode of the diode D44 through the rhcostat R43 and the resistor R31. As long as the diode D44 which comprises a control means whose conduction is controlled by the operation of the ground current tripping circuit 600 is forward biased and in a substantially conducting condition, the timing capacitor Cl0 will not be permitted to accumulate a charge from the positive conductor Pl through the rheostat R43 and the resistor R3! since the current flow from the conductor PI through the rheostat R43 and the resistor R3] will be diverted away from the capacitor C10 to the common conductor NI through the diode D44 and the resistor R30. It is to be noted that as long as the transistor Q14 remains in a substantially nonconducting condition, the capacitor C9 will charge up to a voltage which is equal to the voltage difference between the conductors P1 and N1 less the relatively low voltage drop across the resistor R30. It is also to be noted that as long as the diode D44 remains forward biased, the voltage at the upper side of the capacitor C10 will be equal to the sum of the forward voltage drop of the diode D44 and the voltage drop across the resistor R30 which is relatively low, so that the diode D43 will be reverse biased or blocked since the voltage at the emitter ofthe transistor 015 is maintained at a posi live voltage with respect to the common conductor N1 by the diode D46, the resistor R35 and the diode D45 which are con nected in series between the emitter of the transistor Q15 and the positive conductor P3.

In the operation of the ground current tripping circuit 600 when the ground current in the electrical system being protected exceeds substantially a predetermined or threshold value to which said circuit responds and the corresponding unidirectional voltage across the resistor R28 exceeds substantially a predetermined or threshold value, the voltage at the base of the transistor 013 will increase sufficiently in a positive direction to reverse bias the emitter-base circuit of the transistor 013 which will then be actuated to a substantially nonconducting or cutolf condition. When the transistor Q13 is actuated to a substantially nonconducting condition, the current in the emitter-collector path of the transistor 013 will decrease to a negligible value and the current which flows in the resistor R29 will now flow from the positive conductor Pl through the emitter-base circuit ofthe transistor 014. The transistor 014 will then be actuated to a substantially saturated conditionv When the transistor 014 is actuated to a substantially saturated condition, the emitter-collector current of the transistor Q14 will increase to thereby increase the voltage drop across the resistor R30 and to reverse bias or block the diode D44 which will then permit the timing capacitor C10 to start accumulating a charge from the positive conductor P1 through the rhcostat R43 and the resistor R31. lf permitted to do so by the continuing of the ground current to exceed the predetermined or threshold value, the voltage across the tim' ing capacitor Cl will gradually increase after a predetermined time delay to a value which is suflicient to forward bias the diode D43. It is to be noted that since the charging of the capacitor C is from the regulated voltage at the conductor P1 through the rheostat R43 and the resistor R31, the time delay provided by the time delay circuit 620 will be substantially a predetermined or fixed value after the charging of the capacitor C10 is started by the operation of the level detecting circuit 610 asjust described. When the diode D43 is forward biased by the voltage across the timing capacitor C10, a current will flow from the positive conductor Pl through the rheostat R43, the resistor R31 and the diode D43 to the emitter of the transistor Q which forms part of the output level detecting circuit 410 of the output circuit 400 which will then be actuated to energize the trip coil 36 of the circuit breaker CB and to actuate said circuit breaker to an open condition, as previously described in detail in connection with the long time delay tripping circuit 200 If the ground current exceeds the predetermined or threshold value necessary to actuate the transistor Q14 to a substantially saturated condition as just described, the capacitor C9 which is connected between the emitter and the collector of the transistor 014 will be rapidly discharged through the emitter-collector path of the transistor 014. If the ground current exceeds the predetermined or threshold value necessary to actuate the transistor 014 to substantially a saturated position and then instantaneously decreases below the predetermined or threshold value, the capacitor C9 will gradually charge through the resistor R30 until the voltage at the cathode of the diode D44 decreases --due to the decreasing voltage drop across the resistor R30 sufficiently to forward bias the diode D44 to thereby rapidly discharge or reset the timing capacitor C10 if the voltage across the capacitor C10 has not yet reached the value necessary to forward bias the diode 043 The time delay in the resetting of the ground current tripping circuit 600 following the end ofa ground current which exceeded the predetermined value to which the level detecting circuit 610 responds to thereby actuate the operation of the level detecting circuit 610 is for a time period which may be slightly longer than one-half cycle of the alter nating current which flows in the conductors L1, L2 and L3 and is determined by the values of the capacitor C9 and the re sistor R30 and the voltage between the conductors P1 and N1. In other words, if the ground current in the circuit being protected exceeds the predetermined or threshold value and then continues without an interruption longer than the resetting time delay of the level detecting circuit 610 the charging of the capacitor C10 will continue in an uninterrupted manner until the fixed time delay of the ground current tripping circuit 600. as determined by the time delay circuit 620 is completed. It is to be noted that the predetermined time delay provided by the time delay circuit 620 of the ground current tripping circuit 600 may be varied between minimum and maximum values by the adjustment or setting of the rhcostat R43 which forms part of the time delay circuit 620.

As previously mentioned, it is to be noted that in the operation of the ground current tripping circuit 600, each time that the transistor 014 is actuated from a substantially nonconducting condition to substantially a saturated condition in response to a predetermined ground current occuring in the electrical system being protected, the voltage drop across the resistor R30 which increases with increased current flow in the emitter-collector path of the transistor 014 results in a higher positivc voltage at the anode of the diode D42 with respect to the conductor N] which is transmitted to the base of the transistor 010 through the diode D42 and which reverse biases the emitter-base circuit of the transistor Q10 and actuates the transistor 010 to a substantially noncond uct ing or cutoff condition. This operation prevents the control means 270 which comprises the transistor 010 form forming a low resistance path to the common conductor N1 which would otherwise divert the output current from the ground current tripping circuit 600 away from the emitter of the transistor 015 which is connected to the emitter of the transistor 010 through the diode D35 to thereby prevent the ground current tripping circuit 600 from actuating the opera tion of the output circuit 400. This circuit arrangement is necessary since the level detecting circuit 260 of the long time delay tripping circuit 200 may not actuate the control means 270 which comprises the transistor Q10 to a substantially nonconducting condition even through the ground current in the electrical system which includes the conductors L1, L2 and L3 may have reached a predetermined ground current flow which is sufficient to actuate the operation of the ground current tripping circuit 600 where provided. It is to be noted that the control means 270 which comprises the transistor O10 would necessarily be actuated to a substantially nonconducting condition prior to the operation of either the instantaneous gripping circuit 300 or the short delay tripping circuit 500 where provided since the predetermined current to which the instantaneous tripping circuit 300 responds with the predetermined current to which the short delay tripping circuit 500 responds is greater than and determines the upper limit of the range of overload currents to which the long time delay tripping circuit 200 responds.

It is important to note that the level detecting circuit 260 of the long time delay tripping circuit 200, the level detecting circuit or means 510 of the short delay tripping circuit 500 and the level detecting circuit 610 of the ground current tripping circuit 600 asjust described are all of the same type which was described in greater detail in connection with the long time delay tripping circuit in that each of said level detecting circuits includes a reset operation of the time delay type in order 

1. An overcurrent protective device comprising first means adapted to be connected to an alternating current circuit for deriving therefrom unidirectional output voltage pulses having substantially the same configuration as the half wave portions of the alternating current in said circuit and a magnitude which is substantially directly proportional to that of the current in said circuit, level detecting means connected to said first means for producing a first output substantially instantaneously when the magnitude of said output pulses exceeds substantially a predetermined value, second means adapted to be connected to said alternating current circuit and to said level detecting means for producing a second output after a predetermined time delay which is actuated to start and to continue by said first output, said level detecting means including a timing circuit for maintaining said first output for a predetermined time interval when the magnitude of said output pulses decreases below said predetermined value after exceeding said predetermined value.
 2. The device as claimed in claim 1 wherein said predetermined time interval is slightly longer than one-half cycle of the alternating current in said alternating current circuit.
 3. The device as claimed in claim 1 wherein said level detecting means includes a control means connected to said second means for normally preventing said second means from producing said second output until said level detecting means produces said first output to start said predetermined time delay and continues said first output until the end of said predetermined time delay.
 4. An overcurrent protective device comprising first means adapted to be connected to an alternating current circuit for deriving tHerefrom unidirectional output voltage pulses having substantially the same configuration as the half-wave portions of the alternating current in said circuit and a magnitude which is substantially proportional to that of the current in said circuit, a capacitor for accumulating a charge, second means connected between said circuit and said capacitor for charging said capacitor, level detecting means connected between said first means and said capacitor to be responsive to the magnitude of said output pulses and including control means for normally preventing said second means from charging said capacitor until the magnitude of said output pulses exceeds substantially a predetermined value, third means connected to said capacitor for producing an output when the charge on said capacitor increases to a predetermined level after a predetermined time delay which is initiated by said level detecting means when the magnitude of said output pulses exceeds substantially said predetermined value, said level detecting means including a timing circuit connected to said control means for actuating said control means to permit said capacitor to continue charging for a predetermined time interval when the magnitude of said output pulses decreases below said predetermined value after exceeding said predetermined value.
 5. The device as claimed in claim 4 wherein said time interval is slightly longer than one-half cycle of the alternating current in said alternating current circuit.
 6. The device as claimed in claim 4 wherein an additional means is connected to said first means and to said third means for independently actuating said third means to produce an output substantially instantaneously when the magnitude of said output pulse exceeds substantially a predetermined value which is relatively larger than the predetermined value to which said level detecting means responds to initiate said predetermined time delay.
 7. The device as claimed in claim 4 wherein said timing circuit comprises a resistor and a capacitor connected to a source of unidirectional voltage and to said control means to maintain said control means substantially nonconducting for said predetermined time interval when the magnitude of said output pulses decreases below said predetermined value after exceeding said predetermined value.
 8. A polyphase overcurrent protective device comprising first means adapted to be connected to all three phases of a three-phase alternating circuit for deriving therefrom unidirectional output voltage pulses having substantially the same configuration as the half-wave portions of the alternating current in said circuit and a magnitude which is substantially directly proportional only to the highest of the three-phase currents in said circuit, level detecting means responsive to the magnitude of said output pulses for producing a first output substantially instantaneously when the magnitude of said output pulses exceeds substantially a predetermined value, second means adapted to be connected to said circuit and to said level detecting means for producing a second output after a predetermined time delay which is actuated to start and to continue by said first output, said level detecting means including a timing circuit for maintaining said first output for a predetermined time interval when the magnitude of said output pulses decreases below said predetermined value after exceeding said predetermined value.
 9. The device as claimed in claim 8 wherein said predetermined time interval is slightly larger than one-half cycle of the alternating current in said alternating current circuit.
 10. The device as claimed in claim 9 wherein an additional means is connected to said first means and to said second means for independently actuating said second means to produce said second output substantially instantaneously when the magnitude of said output pulses exceeds substantially a second predetermined value which is relatively larger than the predetermined value to which said level deTecting means responds to produce said first output.
 11. A circuit breaker for use with an alternating current circuit comprising separable contacts adapted to be connected to said circuit, operating means for opening said contacts, and an overcurrent protective device operatively connected to said operating means and responsive to the current in said circuit for producing an output to actuate said operating means to open said contacts, said protective device comprising first means adapted to be connected to said circuit for deriving therefrom unidirectional output voltage pulses having substantially the same configuration as the half-wave portions of the alternating current in said circuit and a magnitude which is substantially directly portional to that of the current in said circuit, level detecting means connected to said first means for producing a first output substantially instantaneously when the magnitude of said output pulses exceeds substantially a predetermined value, second means adapted to be connected to said circuit and to said level detecting means for producing a second output after a predetermined time delay which is actuated to start and to continue by said first output, said level detecting circuit including a timing circuit for maintaining said first output for a predetermined time interval when the magnitude of said output pulses decreases below said predetermined value after exceeding said predetermined value, and third means operatively connected between said second means and said operating means for producing an additional output in response to said second output to actuate said operating means to open said contacts.
 12. The circuit breaker as claimed in claim 11 wherein said predetermined time interval is slightly longer than one-half cycle of the alternating current in said circuit.
 13. The circuit breaker as claimed in claim 11 wherein said level detecting means includes a control means connected to said second means for normally preventing said second means from producing said second output until said level detecting means produces said first output to start said predetermined time delay and continues said first output until the end of said predetermined time delay.
 14. A circuit breaker for use with an alternating current circuit comprising separable contacts adapted to be connected to said circuit, operating means for opening said contacts, and an overcurrent protective device operatively connected to said operating means and responsive to the current in said circuit for producing an output to actuate said operating mean to open said contacts, said protective device comprising first means adapted to be connected to said circuit for deriving therefrom unidirectional output voltage pulses having substantially the same configuration as the half-wave portions of the alternating current in said circuit and a magnitude which is substantially proportional to that of the current in said circuit, a capacitor for accumulating charge, second means connected between said circuit and said capacitor for charging said capacitor, level detecting means connected between said first means and said capacitor to be responsive to the magnitude of said output pulses and including control means for normally preventing said second means from charging said capacitor until the magnitude of said output pulses exceeds substantially a predetermined value, and third means operatively connected between said capacitor and aid operating means for producing an output when the charge on said capacitor increases to a predetermined level after a predetermined time delay which is initiated by said level detecting means when the magnitude of said output pulses exceeds substantially said predetermined value to thereby actuate said operating means to open said contacts, said level detecting means including a timing circuit connected to said control means for actuating said control means to permit said capacitor to continue charging for a predetermined time interval when thE magnitude of said output pulses decreases below said predetermined value after exceeding said predetermined value.
 15. The circuit breaker as claimed in claim 14 wherein said time interval is slightly longer than one-half cycle of the alternating current in said circuit.
 16. The combination as claimed in claim 14 wherein an additional means is connected to said first means and to said third means for independently actuating said third means to produce an output substantially instantaneously when the magnitude of said output pulses exceeds substantially a predetermined value which is relatively larger than the predetermined value to which said level detecting means responds to initiate said predetermined time delay.
 17. The circuit breaker as claimed in claim 14 wherein said timing circuit comprising a resistor and a capacitor connected to a source of unidirectional voltage and to said control means to maintain said control means substantially nonconducting for said predetermined time interval when the magnitude of said output pulses decreases below said predetermined value after exceeding said predetermined value to thereby permit said capacitor to continue charging during said predetermined time interval.
 18. A circuit breaker for use with a three-phase alternating current circuit comprising three sets of separable contacts adapted to be connected to said circuits, operating means for opening said sets of contacts, and an overcurrent protective device operatively connected to said operating means and responsive to the currents in said circuit for producing an output to actuate said operating means to open said sets of contacts, said protective device comprising first means adapted to be connected to said circuit for deriving therefrom unidirectional output voltage pulses having substantially the same configuration as the half-wave portions of the alternating current in said circuit and a magnitude which is substantially proportional to that of the highest of the three-phase currents in said circuit, level detecting means responsive to the magnitude of said output pulses for producing a first output substantially instantaneously when the magnitude of said output pulse exceeds substantially a predetermined value, second means adapted to be connected to said circuit and to said level detecting means for producing a second output after a predetermined time delay which is actuated to start and to continue by said first output, said level detecting means including a timing circuit for maintaining said first output for a predetermined time interval when the magnitude of said output pulses decreases below said predetermined value after exceeding said predetermined value, and third means operatively connected between said second means and said operating means for producing an additional output in response to said second output to actuate said operating means to open said three sets of contacts.
 19. The circuit breaker as claimed in claim 18 wherein said predetermined time interval is slightly longer than one-half cycle of the alternating current in said alternating current circuit.
 20. The circuit breaker as claimed in claim 18 wherein an additional means is connected to said first means and to said third means for independently actuating said third means to produce said additional output substantially instantaneously when the magnitude of said output pulses exceeds substantially a second predetermined value which is relatively larger than the predetermined value to which said level detecting means responds to produce said first output. 